[6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: cluster_header_sync.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | // The sync pulse cluster header is instatiated as a hard macro. |
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| 22 | // This model is for simulation only. |
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| 23 | |
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| 24 | module cluster_header_sync (/*AUTOARG*/ |
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| 25 | // Outputs |
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| 26 | dram_rx_sync_local, dram_tx_sync_local, jbus_rx_sync_local, |
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| 27 | jbus_tx_sync_local, so, |
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| 28 | // Inputs |
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| 29 | dram_rx_sync_global, dram_tx_sync_global, jbus_rx_sync_global, |
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| 30 | jbus_tx_sync_global, cmp_gclk, cmp_rclk, si, se |
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| 31 | ); |
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| 32 | |
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| 33 | output dram_rx_sync_local; |
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| 34 | output dram_tx_sync_local; |
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| 35 | output jbus_rx_sync_local; |
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| 36 | output jbus_tx_sync_local; |
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| 37 | output so; |
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| 38 | |
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| 39 | input dram_rx_sync_global; |
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| 40 | input dram_tx_sync_global; |
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| 41 | input jbus_rx_sync_global; |
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| 42 | input jbus_tx_sync_global; |
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| 43 | input cmp_gclk; |
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| 44 | input cmp_rclk; |
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| 45 | input si; |
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| 46 | input se; |
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| 47 | |
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| 48 | wire dram_rx_so; |
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| 49 | wire dram_tx_so; |
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| 50 | wire jbus_rx_so; |
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| 51 | |
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| 52 | bw_clk_cclk_sync sync_wrapper ( |
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| 53 | .dram_rx_sync_local(dram_rx_sync_local), |
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| 54 | .dram_tx_sync_local(dram_tx_sync_local), |
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| 55 | .jbus_rx_sync_local(jbus_rx_sync_local), |
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| 56 | .jbus_tx_sync_local(jbus_tx_sync_local), |
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| 57 | .so(so), |
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| 58 | .dram_rx_sync_global(dram_rx_sync_global), |
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| 59 | .dram_tx_sync_global(dram_tx_sync_global), |
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| 60 | .jbus_rx_sync_global(jbus_rx_sync_global), |
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| 61 | .jbus_tx_sync_global(jbus_tx_sync_global), |
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| 62 | .cmp_gclk(cmp_gclk), |
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| 63 | .cmp_rclk(cmp_rclk), |
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| 64 | .si(si), |
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| 65 | .se(se) |
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| 66 | ); |
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| 67 | |
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| 68 | endmodule // cluster_header_sync |
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