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bw_r_l2t.v @ 6

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1	// ========== Copyright Header Begin ==========================================
2	//
3	// OpenSPARC T1 Processor File: bw_r_l2t.v
4	// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6	//
7	// The above named program is free software; you can redistribute it and/or
8	// modify it under the terms of the GNU General Public
9	// License version 2 as published by the Free Software Foundation.
10	//
11	// The above named program is distributed in the hope that it will be
12	// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	// General Public License for more details.
15	//
16	// You should have received a copy of the GNU General Public
17	// License along with this work; if not, write to the Free Software
18	// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19	//
20	// ========== Copyright Header End ============================================
21	////////////////////////////////////////////////////////////////////////
22	// Local header file includes / local define
23	// The sctag_pcx*** signals need to be appropriately bound in the
24	// instantiation made in sctag.v
25	////////////////////////////////////////////////////////////////////////
26
27	module bw_r_l2t( /AUTOARG/
28	// Outputs
29	so, l2t_fuse_repair_value, l2t_fuse_repair_en, way_sel, way_sel_1,
30	tag_way0, tag_way1, tag_way2, tag_way3, tag_way4, tag_way5,
31	tag_way6, tag_way7, tag_way8, tag_way9, tag_way10, tag_way11,
32	// Inputs
33	index, bist_index, rd_en, bist_rd_en, way, bist_way, wr_en,
34	bist_wr_en, wrdata0, bist_wrdata0, wrdata1, bist_wrdata1,
35	lkup_tag_d1, rclk, fuse_l2t_wren, fuse_l2t_rid,
36	fuse_l2t_repair_value, fuse_l2t_repair_en, efc_sctag_fuse_clk1,
37	rst_tri_en, si, se, arst_l, sehold
38	);
39
40	// select xbar
41
42	input [9:0] index ; // from addrdp
43	input [9:0] bist_index ; // BIST INPUT
44
45
46	input rd_en ; // enable from arbctl is speculatively asserted.
47	input bist_rd_en ; // BIST INPUT
48
49	input [11:0] way; // way for a fill/tag write
50	input [11:0] bist_way;// BIST INPUT
51
52	input wr_en; // on a fill in px2 or a diag/tecc write.
53	input bist_wr_en ; // BIST INPUT
54
55	input [27:0] wrdata0 ; // wr tag
56	input [7:0] bist_wrdata0 ; // wr tag
57	input [27:0] wrdata1 ; // wr tag
58	input [7:0] bist_wrdata1 ; // wr tag
59
60	input [27:1] lkup_tag_d1 ; //ecc bits are appended to this tag.
61
62	input rclk;
63
64	// input [3:0] tag_stm ; ?? may not be needed.
65
66
67	input fuse_l2t_wren; //redundancy reg wr enable, qualified
68	input [5:0] fuse_l2t_rid; //redundancy register id <5:2> == subbank, <1:0> determines row/col red.
69	input [6:0] fuse_l2t_repair_value; //data in for redundancy register
70	input [1:0] fuse_l2t_repair_en; //enable bits to turn on redundancy
71	input efc_sctag_fuse_clk1;
72
73
74
75
76	input rst_tri_en;
77	input si, se;
78	output so;
79	input arst_l;
80	input sehold;
81
82	output [6:0] l2t_fuse_repair_value; //data out for redundancy register
83	output [1:0] l2t_fuse_repair_en; //enable bits out
84
85	output [11:0] way_sel; // compare outputs
86	output [11:0] way_sel_1; // compare outputs
87
88	output [27:0] tag_way0;
89	output [27:0] tag_way1;
90	output [27:0] tag_way2;
91	output [27:0] tag_way3;
92	output [27:0] tag_way4;
93	output [27:0] tag_way5;
94	output [27:0] tag_way6;
95	output [27:0] tag_way7;
96	output [27:0] tag_way8;
97	output [27:0] tag_way9;
98	output [27:0] tag_way10;
99	output [27:0] tag_way11;
100
101	reg [27:0] wrdata0_d1_l, wrdata1_d1_l ;
102	wire [11:0] gbl_red_bank_id;
103	reg [6:0] l2t_fuse_repair_value;
104	reg [1:0] l2t_fuse_repair_en;
105
106	wire [6:0] red_reg_q_ab, red_reg_q_89, red_reg_q_67, red_reg_q_45 ;
107	wire [6:0] red_reg_q_01, red_reg_q_23;
108	wire [1:0] red_reg_enq_ab, red_reg_enq_89, red_reg_enq_67, red_reg_enq_45 ;
109	wire [1:0] red_reg_enq_01, red_reg_enq_23;
110	wire [5:0] wr_en_subbank;
111	wire [27:0] tag_wrdata0_px2, tag_wrdata1_px2 ;
112
113	assign tag_wrdata0_px2 = ( bist_wr_en ) ? { bist_wrdata0[3:0],
114	{3{bist_wrdata0[7:0]}} } : wrdata0;
115
116	assign tag_wrdata1_px2 = ( bist_wr_en ) ? { bist_wrdata1[3:0],
117	{3{bist_wrdata1[7:0]}} } : wrdata1;
118
119	// Inputs that are flopped
120
121	always @(posedge rclk) begin
122	wrdata0_d1_l <= (sehold)? wrdata0_d1_l: ~tag_wrdata0_px2 ;
123	wrdata1_d1_l <= (sehold)? wrdata1_d1_l: ~tag_wrdata1_px2 ;
124
125	`ifdef INNO_MUXEX
126	`else
127	//----- PURELY FOR VERIFICATION -----------------------
128	if(wr_en) begin
129	case(way)
130	12'b000000000001: ;
131	12'b000000000010: ;
132	12'b000000000100: ;
133	12'b000000001000: ;
134	12'b000000010000: ;
135	12'b000000100000: ;
136	12'b000001000000: ;
137	12'b000010000000: ;
138	12'b000100000000: ;
139	12'b001000000000: ;
140	12'b010000000000: ;
141	12'b100000000000: ;
142	default:
143	`ifdef MODELSIM
144	$display("L2_TAG_ERR"," way select error %h ", way[11:0]);
145	`else
146	$error("L2_TAG_ERR"," way select error %h ", way[11:0]);
147	`endif
148	endcase
149	end // of if
150	//----- PURELY FOR VERIFICATION -----------------------
151	`endif
152	end
153
154	assign way_sel_1 = way_sel ;
155
156	assign gbl_red_bank_id[0] = ( fuse_l2t_rid[5:2] == 4'd0) ;
157	assign gbl_red_bank_id[1] = ( fuse_l2t_rid[5:2] == 4'd1) ;
158	assign gbl_red_bank_id[2] = ( fuse_l2t_rid[5:2] == 4'd2) ;
159	assign gbl_red_bank_id[3] = ( fuse_l2t_rid[5:2] == 4'd3) ;
160	assign gbl_red_bank_id[4] = ( fuse_l2t_rid[5:2] == 4'd4) ;
161	assign gbl_red_bank_id[5] = ( fuse_l2t_rid[5:2] == 4'd5) ;
162	assign gbl_red_bank_id[6] = ( fuse_l2t_rid[5:2] == 4'd6) ;
163	assign gbl_red_bank_id[7] = ( fuse_l2t_rid[5:2] == 4'd7) ;
164	assign gbl_red_bank_id[8] = ( fuse_l2t_rid[5:2] == 4'd8) ;
165	assign gbl_red_bank_id[9] = ( fuse_l2t_rid[5:2] == 4'd9) ;
166	assign gbl_red_bank_id[10] = ( fuse_l2t_rid[5:2] == 4'd10) ;
167	assign gbl_red_bank_id[11] = ( fuse_l2t_rid[5:2] == 4'd11) ;
168
169
170	//assign wr_en_subbank[0] = fuse_l2t_wren & ( \|(gbl_red_bank_id[1:0]) );
171	//assign wr_en_subbank[1] = fuse_l2t_wren & ( \|(gbl_red_bank_id[5:4]) );
172	//assign wr_en_subbank[2] = fuse_l2t_wren & ( \|(gbl_red_bank_id[9:8]) );
173	//assign wr_en_subbank[3] = fuse_l2t_wren & ( \|(gbl_red_bank_id[3:2]) );
174	//assign wr_en_subbank[4] = fuse_l2t_wren & ( \|(gbl_red_bank_id[7:6]) );
175	//assign wr_en_subbank[5] = fuse_l2t_wren & ( \|(gbl_red_bank_id[11:10]) );
176
177	// JC modified begin
178	// Write enable signal goes directly to subbank without any gating circuits.
179	assign wr_en_subbank[0] = fuse_l2t_wren;
180	assign wr_en_subbank[1] = fuse_l2t_wren;
181	assign wr_en_subbank[2] = fuse_l2t_wren;
182	assign wr_en_subbank[3] = fuse_l2t_wren;
183	assign wr_en_subbank[4] = fuse_l2t_wren;
184	assign wr_en_subbank[5] = fuse_l2t_wren;
185	// JC modified begin
186
187
188
189	always @(/AUTOSENSE/gbl_red_bank_id or red_reg_enq_01
190	or red_reg_enq_23 or red_reg_enq_45 or red_reg_enq_67
191	or red_reg_enq_89 or red_reg_enq_ab or red_reg_q_01
192	or red_reg_q_23 or red_reg_q_45 or red_reg_q_67
193	or red_reg_q_89 or red_reg_q_ab)begin
194
195	case(gbl_red_bank_id)
196
197	12'b000000000001: begin
198	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
199	{ red_reg_enq_01[1:0], red_reg_q_01[6:0] } ;
200	end
201	12'b000000000010: begin
202	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
203	{ red_reg_enq_01[1:0], red_reg_q_01[6:0] } ;
204	end
205	12'b000000000100: begin
206	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
207	{ red_reg_enq_23[1:0], red_reg_q_23[6:0] } ;
208	end
209	12'b000000001000: begin
210	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
211	{ red_reg_enq_23[1:0], red_reg_q_23[6:0] } ;
212	end
213	12'b000000010000: begin
214	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
215	{ red_reg_enq_45[1:0], red_reg_q_45[6:0] } ;
216	end
217	12'b000000100000: begin
218	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
219	{ red_reg_enq_45[1:0], red_reg_q_45[6:0] } ;
220	end
221	12'b000001000000: begin
222	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
223	{ red_reg_enq_67[1:0], red_reg_q_67[6:0] } ;
224	end
225	12'b000010000000: begin
226	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
227	{ red_reg_enq_67[1:0], red_reg_q_67[6:0] } ;
228	end
229	12'b000100000000: begin
230	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
231	{ red_reg_enq_89[1:0], red_reg_q_89[6:0] } ;
232	end
233	12'b001000000000: begin
234	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
235	{ red_reg_enq_89[1:0], red_reg_q_89[6:0] } ;
236	end
237	12'b010000000000: begin
238	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
239	{ red_reg_enq_ab[1:0], red_reg_q_ab[6:0] } ;
240	end
241	12'b100000000000: begin
242	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} =
243	{ red_reg_enq_ab[1:0], red_reg_q_ab[6:0] } ;
244	end
245
246	default: begin
247	// JC added begin
248	// remove implicit latch.
249	{ l2t_fuse_repair_en[1:0], l2t_fuse_repair_value[6:0]} = 9'b0;
250	// JCadded end
251
252	end
253
254	endcase
255
256	end
257
258	/* bw_r_l2t_subbank AUTO_TEMPLATE (
259	// Outputs
260	.wayselect0 (way_sel[0]),
261	.wayselect1 (way_sel[1]),
262	.tag_way0 (tag_way0[27:0]),
263	.tag_way1 (tag_way1[27:0]),
264	.red_reg_q_array2(red_reg_q_01[6:0]),
265	.red_reg_enq_array2(red_reg_enq_01[1:0]),
266	// Inputs
267	.way (way[1:0]),
268	.bist_way (bist_way[1:0]),
269	.wd_b_l (wrdata0_d1_l[27:0]),
270	.lkuptag (lkup_tag_d1[27:1]),
271	.rclk (rclk),
272	.sehold (sehold),
273	.se (se),
274	.sin (),
275	.sout (),
276	.rst_tri_en (rst_tri_en),
277	.arst_l (arst_l),
278	.gbl_red_rid(fuse_l2t_rid[1:0]),
279	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
280	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
281	.fclk1 (efc_sctag_fuse_clk1),
282	.gbl_red_bank_id_top(gbl_red_bank_id[0]),
283	.gbl_red_bank_id_bottom(gbl_red_bank_id[1]),
284	.gbl_red_wr_en(wr_en_subbank[0]));
285
286	*/
287
288	bw_r_l2t_subbank subbank01(/AUTOINST/
289	// Outputs
290	.sout (), // Templated
291	.wayselect0(way_sel[0]), // Templated
292	.wayselect1(way_sel[1]), // Templated
293	.tag_way0 (tag_way0[27:0]), // Templated
294	.tag_way1 (tag_way1[27:0]), // Templated
295	.red_reg_q_array2(red_reg_q_01[6:0]), // Templated
296	.red_reg_enq_array2(red_reg_enq_01[1:0]), // Templated
297	// Inputs
298	.index (index[9:0]),
299	.bist_index(bist_index[9:0]),
300	.wr_en (wr_en),
301	.bist_wr_en(bist_wr_en),
302	.rd_en (rd_en),
303	.bist_rd_en(bist_rd_en),
304	.way (way[1:0]), // Templated
305	.bist_way (bist_way[1:0]), // Templated
306	.wd_b_l (wrdata0_d1_l[27:0]), // Templated
307	.lkuptag (lkup_tag_d1[27:1]), // Templated
308	.rclk (rclk), // Templated
309	.sehold (sehold), // Templated
310	.se (se), // Templated
311	.sin (), // Templated
312	.rst_tri_en(rst_tri_en), // Templated
313	.arst_l (arst_l), // Templated
314	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
315	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
316	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
317	.fclk1 (efc_sctag_fuse_clk1), // Templated
318	.gbl_red_bank_id_top(gbl_red_bank_id[0]), // Templated
319	.gbl_red_bank_id_bottom(gbl_red_bank_id[1]), // Templated
320	.gbl_red_wr_en(wr_en_subbank[0])); // Templated
321
322	/* bw_r_l2t_subbank AUTO_TEMPLATE (
323	// Outputs
324	.wayselect0 (way_sel[4]),
325	.wayselect1 (way_sel[5]),
326	.tag_way0 (tag_way4[27:0]),
327	.tag_way1 (tag_way5[27:0]),
328	.red_reg_q_array2(red_reg_q_45[6:0]),
329	.red_reg_enq_array2(red_reg_enq_45[1:0]),
330	// Inputs
331	.way (way[5:4]),
332	.bist_way (bist_way[5:4]),
333	.wd_b_l (wrdata0_d1_l[27:0]),
334	.lkuptag (lkup_tag_d1[27:1]),
335	.rclk (rclk),
336	.sehold (sehold),
337	.se (se),
338	.sin (),
339	.sout (),
340	.rst_tri_en (rst_tri_en),
341	.arst_l (arst_l),
342	.gbl_red_rid(fuse_l2t_rid[1:0]),
343	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
344	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
345	.fclk1 (efc_sctag_fuse_clk1),
346	.gbl_red_bank_id_top(gbl_red_bank_id[4]),
347	.gbl_red_bank_id_bottom(gbl_red_bank_id[5]),
348	.gbl_red_wr_en(wr_en_subbank[1]));
349
350	*/
351
352	bw_r_l2t_subbank subbank45(/AUTOINST/
353	// Outputs
354	.sout (), // Templated
355	.wayselect0(way_sel[4]), // Templated
356	.wayselect1(way_sel[5]), // Templated
357	.tag_way0 (tag_way4[27:0]), // Templated
358	.tag_way1 (tag_way5[27:0]), // Templated
359	.red_reg_q_array2(red_reg_q_45[6:0]), // Templated
360	.red_reg_enq_array2(red_reg_enq_45[1:0]), // Templated
361	// Inputs
362	.index (index[9:0]),
363	.bist_index(bist_index[9:0]),
364	.wr_en (wr_en),
365	.bist_wr_en(bist_wr_en),
366	.rd_en (rd_en),
367	.bist_rd_en(bist_rd_en),
368	.way (way[5:4]), // Templated
369	.bist_way (bist_way[5:4]), // Templated
370	.wd_b_l (wrdata0_d1_l[27:0]), // Templated
371	.lkuptag (lkup_tag_d1[27:1]), // Templated
372	.rclk (rclk), // Templated
373	.sehold (sehold), // Templated
374	.se (se), // Templated
375	.sin (), // Templated
376	.rst_tri_en(rst_tri_en), // Templated
377	.arst_l (arst_l), // Templated
378	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
379	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
380	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
381	.fclk1 (efc_sctag_fuse_clk1), // Templated
382	.gbl_red_bank_id_top(gbl_red_bank_id[4]), // Templated
383	.gbl_red_bank_id_bottom(gbl_red_bank_id[5]), // Templated
384	.gbl_red_wr_en(wr_en_subbank[1])); // Templated
385
386	/* bw_r_l2t_subbank AUTO_TEMPLATE (
387	// Outputs
388	.wayselect0 (way_sel[8]),
389	.wayselect1 (way_sel[9]),
390	.tag_way0 (tag_way8[27:0]),
391	.tag_way1 (tag_way9[27:0]),
392	.red_reg_q_array2(red_reg_q_89[6:0]),
393	.red_reg_enq_array2(red_reg_enq_89[1:0]),
394	// Inputs
395	.way (way[9:8]),
396	.bist_way (bist_way[9:8]),
397	.wd_b_l (wrdata0_d1_l[27:0]),
398	.lkuptag (lkup_tag_d1[27:1]),
399	.rclk (rclk),
400	.sehold (sehold),
401	.se (se),
402	.sin (),
403	.sout (),
404	.rst_tri_en (rst_tri_en),
405	.arst_l (arst_l),
406	.gbl_red_rid(fuse_l2t_rid[1:0]),
407	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
408	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
409	.fclk1 (efc_sctag_fuse_clk1),
410	.gbl_red_bank_id_top(gbl_red_bank_id[8]),
411	.gbl_red_bank_id_bottom(gbl_red_bank_id[9]),
412	.gbl_red_wr_en(wr_en_subbank[2]));
413
414	*/
415
416
417	bw_r_l2t_subbank subbank89(/AUTOINST/
418	// Outputs
419	.sout (), // Templated
420	.wayselect0(way_sel[8]), // Templated
421	.wayselect1(way_sel[9]), // Templated
422	.tag_way0 (tag_way8[27:0]), // Templated
423	.tag_way1 (tag_way9[27:0]), // Templated
424	.red_reg_q_array2(red_reg_q_89[6:0]), // Templated
425	.red_reg_enq_array2(red_reg_enq_89[1:0]), // Templated
426	// Inputs
427	.index (index[9:0]),
428	.bist_index(bist_index[9:0]),
429	.wr_en (wr_en),
430	.bist_wr_en(bist_wr_en),
431	.rd_en (rd_en),
432	.bist_rd_en(bist_rd_en),
433	.way (way[9:8]), // Templated
434	.bist_way (bist_way[9:8]), // Templated
435	.wd_b_l (wrdata0_d1_l[27:0]), // Templated
436	.lkuptag (lkup_tag_d1[27:1]), // Templated
437	.rclk (rclk), // Templated
438	.sehold (sehold), // Templated
439	.se (se), // Templated
440	.sin (), // Templated
441	.rst_tri_en(rst_tri_en), // Templated
442	.arst_l (arst_l), // Templated
443	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
444	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
445	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
446	.fclk1 (efc_sctag_fuse_clk1), // Templated
447	.gbl_red_bank_id_top(gbl_red_bank_id[8]), // Templated
448	.gbl_red_bank_id_bottom(gbl_red_bank_id[9]), // Templated
449	.gbl_red_wr_en(wr_en_subbank[2])); // Templated
450
451	/* bw_r_l2t_subbank AUTO_TEMPLATE (
452	// Outputs
453	.wayselect0 (way_sel[2]),
454	.wayselect1 (way_sel[3]),
455	.tag_way0 (tag_way2[27:0]),
456	.tag_way1 (tag_way3[27:0]),
457	.red_reg_q_array2(red_reg_q_23[6:0]),
458	.red_reg_enq_array2(red_reg_enq_23[1:0]),
459	// Inputs
460	.way (way[3:2]),
461	.bist_way (bist_way[3:2]),
462	.wd_b_l (wrdata1_d1_l[27:0]),
463	.lkuptag (lkup_tag_d1[27:1]),
464	.rclk (rclk),
465	.sehold (sehold),
466	.se (se),
467	.sin (),
468	.sout (),
469	.rst_tri_en (rst_tri_en),
470	.arst_l (arst_l),
471	.gbl_red_rid(fuse_l2t_rid[1:0]),
472	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
473	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
474	.fclk1 (efc_sctag_fuse_clk1),
475	.gbl_red_bank_id_top(gbl_red_bank_id[2]),
476	.gbl_red_bank_id_bottom(gbl_red_bank_id[3]),
477	.gbl_red_wr_en(wr_en_subbank[3]));
478
479	*/
480
481	bw_r_l2t_subbank subbank23(/AUTOINST/
482	// Outputs
483	.sout (), // Templated
484	.wayselect0(way_sel[2]), // Templated
485	.wayselect1(way_sel[3]), // Templated
486	.tag_way0 (tag_way2[27:0]), // Templated
487	.tag_way1 (tag_way3[27:0]), // Templated
488	.red_reg_q_array2(red_reg_q_23[6:0]), // Templated
489	.red_reg_enq_array2(red_reg_enq_23[1:0]), // Templated
490	// Inputs
491	.index (index[9:0]),
492	.bist_index(bist_index[9:0]),
493	.wr_en (wr_en),
494	.bist_wr_en(bist_wr_en),
495	.rd_en (rd_en),
496	.bist_rd_en(bist_rd_en),
497	.way (way[3:2]), // Templated
498	.bist_way (bist_way[3:2]), // Templated
499	.wd_b_l (wrdata1_d1_l[27:0]), // Templated
500	.lkuptag (lkup_tag_d1[27:1]), // Templated
501	.rclk (rclk), // Templated
502	.sehold (sehold), // Templated
503	.se (se), // Templated
504	.sin (), // Templated
505	.rst_tri_en(rst_tri_en), // Templated
506	.arst_l (arst_l), // Templated
507	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
508	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
509	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
510	.fclk1 (efc_sctag_fuse_clk1), // Templated
511	.gbl_red_bank_id_top(gbl_red_bank_id[2]), // Templated
512	.gbl_red_bank_id_bottom(gbl_red_bank_id[3]), // Templated
513	.gbl_red_wr_en(wr_en_subbank[3])); // Templated
514
515	/* bw_r_l2t_subbank AUTO_TEMPLATE (
516	// Outputs
517	.wayselect0 (way_sel[6]),
518	.wayselect1 (way_sel[7]),
519	.tag_way0 (tag_way6[27:0]),
520	.tag_way1 (tag_way7[27:0]),
521	.red_reg_q_array2(red_reg_q_67[6:0]),
522	.red_reg_enq_array2(red_reg_enq_67[1:0]),
523	// Inputs
524	.way (way[7:6]),
525	.bist_way (bist_way[7:6]),
526	.wd_b_l (wrdata1_d1_l[27:0]),
527	.lkuptag (lkup_tag_d1[27:1]),
528	.rclk (rclk),
529	.sehold (sehold),
530	.se (se),
531	.sin (),
532	.sout (),
533	.rst_tri_en (rst_tri_en),
534	.arst_l (arst_l),
535	.gbl_red_rid(fuse_l2t_rid[1:0]),
536	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
537	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
538	.fclk1 (efc_sctag_fuse_clk1),
539	.gbl_red_bank_id_top(gbl_red_bank_id[6]),
540	.gbl_red_bank_id_bottom(gbl_red_bank_id[7]),
541	.gbl_red_wr_en(wr_en_subbank[4]));
542
543	*/
544
545	bw_r_l2t_subbank subbank67(/AUTOINST/
546	// Outputs
547	.sout (), // Templated
548	.wayselect0(way_sel[6]), // Templated
549	.wayselect1(way_sel[7]), // Templated
550	.tag_way0(tag_way6[27:0]), // Templated
551	.tag_way1(tag_way7[27:0]), // Templated
552	.red_reg_q_array2(red_reg_q_67[6:0]), // Templated
553	.red_reg_enq_array2(red_reg_enq_67[1:0]), // Templated
554	// Inputs
555	.index(index[9:0]),
556	.bist_index(bist_index[9:0]),
557	.wr_en(wr_en),
558	.bist_wr_en(bist_wr_en),
559	.rd_en(rd_en),
560	.bist_rd_en(bist_rd_en),
561	.way (way[7:6]), // Templated
562	.bist_way(bist_way[7:6]), // Templated
563	.wd_b_l(wrdata1_d1_l[27:0]), // Templated
564	.lkuptag(lkup_tag_d1[27:1]), // Templated
565	.rclk (rclk), // Templated
566	.sehold(sehold), // Templated
567	.se (se), // Templated
568	.sin (), // Templated
569	.rst_tri_en(rst_tri_en), // Templated
570	.arst_l(arst_l), // Templated
571	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
572	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
573	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
574	.fclk1(efc_sctag_fuse_clk1), // Templated
575	.gbl_red_bank_id_top(gbl_red_bank_id[6]), // Templated
576	.gbl_red_bank_id_bottom(gbl_red_bank_id[7]), // Templated
577	.gbl_red_wr_en(wr_en_subbank[4])); // Templated
578
579	/* bw_r_l2t_subbank AUTO_TEMPLATE (
580	// Outputs
581	.wayselect0 (way_sel[10]),
582	.wayselect1 (way_sel[11]),
583	.tag_way0 (tag_way10[27:0]),
584	.tag_way1 (tag_way11[27:0]),
585	.red_reg_q_array2(red_reg_q_ab[6:0]),
586	.red_reg_enq_array2(red_reg_enq_ab[1:0]),
587	// Inputs
588	.way (way[11:10]),
589	.bist_way (bist_way[11:10]),
590	.wd_b_l (wrdata1_d1_l[27:0]),
591	.lkuptag (lkup_tag_d1[27:1]),
592	.rclk (rclk),
593	.sehold (sehold),
594	.se (se),
595	.sin (),
596	.sout (),
597	.rst_tri_en (rst_tri_en),
598	.arst_l (arst_l),
599	.gbl_red_rid(fuse_l2t_rid[1:0]),
600	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]),
601	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]),
602	.fclk1 (efc_sctag_fuse_clk1),
603	.gbl_red_bank_id_top(gbl_red_bank_id[10]),
604	.gbl_red_bank_id_bottom(gbl_red_bank_id[11]),
605	.gbl_red_wr_en(wr_en_subbank[5]));
606
607	*/
608
609	bw_r_l2t_subbank subbankab(/AUTOINST/
610	// Outputs
611	.sout (), // Templated
612	.wayselect0(way_sel[10]), // Templated
613	.wayselect1(way_sel[11]), // Templated
614	.tag_way0(tag_way10[27:0]), // Templated
615	.tag_way1(tag_way11[27:0]), // Templated
616	.red_reg_q_array2(red_reg_q_ab[6:0]), // Templated
617	.red_reg_enq_array2(red_reg_enq_ab[1:0]), // Templated
618	// Inputs
619	.index(index[9:0]),
620	.bist_index(bist_index[9:0]),
621	.wr_en(wr_en),
622	.bist_wr_en(bist_wr_en),
623	.rd_en(rd_en),
624	.bist_rd_en(bist_rd_en),
625	.way (way[11:10]), // Templated
626	.bist_way(bist_way[11:10]), // Templated
627	.wd_b_l(wrdata1_d1_l[27:0]), // Templated
628	.lkuptag(lkup_tag_d1[27:1]), // Templated
629	.rclk (rclk), // Templated
630	.sehold(sehold), // Templated
631	.se (se), // Templated
632	.sin (), // Templated
633	.rst_tri_en(rst_tri_en), // Templated
634	.arst_l(arst_l), // Templated
635	.gbl_red_rid(fuse_l2t_rid[1:0]), // Templated
636	.gbl_red_reg_en(fuse_l2t_repair_en[1:0]), // Templated
637	.gbl_red_reg_d(fuse_l2t_repair_value[6:0]), // Templated
638	.fclk1(efc_sctag_fuse_clk1), // Templated
639	.gbl_red_bank_id_top(gbl_red_bank_id[10]), // Templated
640	.gbl_red_bank_id_bottom(gbl_red_bank_id[11]), // Templated
641	.gbl_red_wr_en(wr_en_subbank[5])); // Templated
642
643
644	endmodule
645
646
647
648
649
650	module bw_r_l2t_subbank(/AUTOARG/
651	// Outputs
652	sout, wayselect0, wayselect1, tag_way0, tag_way1,
653	red_reg_q_array2, red_reg_enq_array2,
654	// Inputs
655	index, bist_index, wr_en, bist_wr_en, rd_en, bist_rd_en, way,
656	bist_way, wd_b_l, lkuptag, rclk, sehold, se, sin, rst_tri_en,
657	arst_l, gbl_red_rid, gbl_red_reg_en, gbl_red_reg_d, fclk1,
658	gbl_red_bank_id_top, gbl_red_bank_id_bottom, gbl_red_wr_en
659	);
660
661	// !!! Changed gbl_red_wren to gbl_red_wr_en as it is in schematic !!!
662
663	//////////////
664	// INPUTS
665	//////////////
666
667	input [9:0] index;
668	input [9:0] bist_index;
669	input wr_en;
670	input bist_wr_en;
671	input rd_en;
672	input bist_rd_en;
673	input [1:0] way;
674	input [1:0] bist_way;
675
676	input [27:0] wd_b_l ; //inverted data. not flopped here
677	input [27:1] lkuptag; //not flopped here
678
679	input rclk;
680	input sehold;
681	input se;
682	input sin;
683	input rst_tri_en;
684
685	// not coded in the spec
686	// arst function
687
688	input arst_l; // redundancy registers.
689
690	input [1:0] gbl_red_rid;
691
692	input [1:0] gbl_red_reg_en;
693	input [6:0] gbl_red_reg_d;
694
695	input fclk1;
696	input gbl_red_bank_id_top;
697	input gbl_red_bank_id_bottom;
698
699	input gbl_red_wr_en ;
700
701	// !!! Changed gbl_red_wren to gbl_red_wr_en as it is in schematic !!!
702
703
704
705	//////////////
706	// OUTPUTS
707	//////////////
708
709	output sout;
710	output wayselect0;
711	output wayselect1;
712
713	output [27:0] tag_way0 ;
714	output [27:0] tag_way1 ;
715
716
717	output [6:0] red_reg_q_array2;
718	output [1:0] red_reg_enq_array2;
719
720	// !!! Taken out ssclk !!!
721
722	// !!! Registering all tag outputs including wayselect as it is how implemented in design !!!
723	wire temp_wayselect0; //Registering wayselect signal
724	wire temp_wayselect1; //Registering wayselect signal
725
726	reg wayselect0; // Registering wayselect signal
727	reg wayselect1; // Registering wayselect signal
728
729	reg [27:0] temp_tag_way0 ; // Registering tag read out data
730	reg [27:0] temp_tag_way1 ; // Registering tag read out data
731	// !!! Registering all tag outputs including wayselect as it is how implemented in design !!!
732
733	reg [9:0] index_d1;
734	reg [1:0] way_d1;
735	reg wren_d1, rden_d1 ;
736	reg [27:0] way0[1023:0] ;
737	reg [27:0] way1[1023:0] ;
738	reg [27:0] tag_way0, tag_way1 ;
739
740	// JC modified begin
741	// the size of row redundant register is 1 bit smaller than
742	// the size of column one.
743	reg [7:0] rid_subbank0_reg0 ;
744	reg [7:0] rid_subbank0_reg1 ;
745	// JC modified end
746	reg [8:0] rid_subbank0_reg2 ;
747	reg [8:0] rid_subbank0_reg3 ;
748
749	// JC modified begin
750	reg [7:0] rid_subbank1_reg0 ;
751	reg [7:0] rid_subbank1_reg1 ;
752	// JC modified end
753
754	reg [8:0] rid_subbank1_reg2 ;
755	reg [8:0] rid_subbank1_reg3 ;
756
757	reg [1:0] red_reg_enq_array2;
758	reg [6:0] red_reg_q_array2;
759	wire [3:0] red_reg;
760
761
762	////////////////////////////
763	// REDUNDANCY LOGIC
764	////////////////////////////
765	assign red_reg = { gbl_red_bank_id_top, gbl_red_bank_id_bottom, gbl_red_rid[1:0] };
766
767	// JC modified begin
768	// The following modification include
769	// 1. the size of row redundant register changes.
770	// 2. the redundant output does not gate with clock
771
772
773
774	always @(posedge fclk1 or arst_l ) begin
775
776	if(!arst_l) begin
777	rid_subbank0_reg0 = 8'b0 ;
778	rid_subbank0_reg1 = 8'b0 ;
779	rid_subbank0_reg2 = 9'b0 ;
780	rid_subbank0_reg3 = 9'b0 ;
781	rid_subbank1_reg0 = 8'b0 ;
782	rid_subbank1_reg1 = 8'b0 ;
783	rid_subbank1_reg2 = 9'b0 ;
784	rid_subbank1_reg3 = 9'b0 ;
785	end
786
787	else if(gbl_red_wr_en) begin
788	case(red_reg)
789
790	4'b1000: rid_subbank0_reg0 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
791
792	4'b1001: rid_subbank0_reg1 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
793
794	4'b1010: rid_subbank0_reg2 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
795
796	4'b1011: rid_subbank0_reg3 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
797
798	4'b0100: rid_subbank1_reg0 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
799
800	4'b0101: rid_subbank1_reg1 = {gbl_red_reg_d[5:0], gbl_red_reg_en[1:0]};
801
802	4'b0110: rid_subbank1_reg2 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
803
804	4'b0111: rid_subbank1_reg3 = {gbl_red_reg_d[6:0], gbl_red_reg_en[1:0]};
805
806	default: ; // Do nothing
807
808	endcase
809	end // of else if
810
811	end // of always
812
813	always @( red_reg or rid_subbank0_reg0 or rid_subbank0_reg1 or rid_subbank0_reg2 or rid_subbank0_reg3 or
814	rid_subbank1_reg0 or rid_subbank1_reg1 or rid_subbank1_reg2 or rid_subbank1_reg3) begin
815
816	case(red_reg)
817
818	4'b1000:
819	{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank0_reg0};
820
821	4'b1001:
822	{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank0_reg1};
823
824	4'b1010:
825	{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank0_reg2;
826
827	4'b1011:
828	{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank0_reg3;
829
830	4'b0100:
831	{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank1_reg0};
832
833	4'b0101:
834	{ red_reg_q_array2, red_reg_enq_array2 } = {1'b0,rid_subbank1_reg1};
835
836	4'b0110:
837	{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank1_reg2;
838
839	4'b0111:
840	{ red_reg_q_array2, red_reg_enq_array2 } = rid_subbank1_reg3;
841
842	default:
843	{ red_reg_q_array2, red_reg_enq_array2 } = 9'b0;
844
845	endcase
846	end
847
848
849	always @(posedge rclk) begin
850
851	index_d1 <= ( sehold) ? index_d1 :
852	( bist_wr_en \| bist_rd_en ) ? bist_index : index ;
853	way_d1 <= (sehold)? way_d1 :
854	( bist_wr_en \| bist_rd_en ) ? bist_way : way ;
855	wren_d1 <= ( sehold)? wren_d1 :
856	( bist_wr_en \| wr_en ) ;
857	rden_d1 <= ( sehold)? rden_d1 :
858	( bist_rd_en \| rd_en );
859
860	end
861
862	// !!! Flopping output signals !!!
863	always @(posedge rclk) begin
864	wayselect0 <= temp_wayselect0;
865	wayselect1 <= temp_wayselect1;
866	tag_way0 <= temp_tag_way0;
867	tag_way1 <= temp_tag_way1;
868	end
869	// !!! Flopping output signals !!!
870
871	////////////////////////////////
872	// COMPARE OPERATION
873	////////////////////////////////
874
875	// !!! Also, we are gating wayselect with rd_en so, in other cycles (write or no op)
876	// all wayselect signals are miss. !!!
877
878	assign temp_wayselect0 = (rden_d1) ? ( lkuptag == temp_tag_way0[27:1] ) : 0 ;
879	assign temp_wayselect1 = (rden_d1) ? ( lkuptag == temp_tag_way1[27:1] ) : 0 ;
880
881	////////////////////////////////
882	// READ OPERATION
883	////////////////////////////////
884	always @( /AUTOSENSE/ /memory or/ index_d1 or rden_d1
885	or rst_tri_en or wren_d1) begin
886
887	`ifdef INNO_MUXEX
888	`else
889	if(wren_d1==1'bx) begin
890	`ifdef MODELSIM
891	$display("L2_TAG_ERR"," wr en error %b ", wren_d1);
892	`else
893	$error("L2_TAG_ERR"," wr en error %b ", wren_d1);
894	`endif
895	end
896	`endif
897
898
899	if( rden_d1) begin
900
901	`ifdef INNO_MUXEX
902	`else
903	//----- PURELY FOR VERIFICATION -----------------------
904	if(index_d1==10'bx) begin
905	`ifdef MODELSIM
906	$display("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
907	`else
908	$error("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
909	`endif
910	end
911	//----- PURELY FOR VERIFICATION -----------------------
912	`endif
913	if( wren_d1 ) begin
914	temp_tag_way0 = 28'bx ;
915	temp_tag_way1 = 28'bx ;
916	end
917	else begin
918	temp_tag_way0 = way0[index_d1] ;
919	temp_tag_way1 = way1[index_d1] ;
920	end
921
922	end // of if rden_d1
923
924	else begin
925	// !!! When Tag is in write or no-op cycles, all output will be "0" since SAs are precharged !!!
926
927	temp_tag_way0 = 0;
928	temp_tag_way1 = 0;
929
930	end
931
932	end
933
934	////////////////////////////////
935	// WRITE OPERATION
936	////////////////////////////////
937	always @(negedge rclk ) begin
938	if( wren_d1 & ~rst_tri_en) begin
939
940	`ifdef INNO_MUXEX
941	`else
942	//----- PURELY FOR VERIFICATION -----------------------
943	if(index_d1==10'bx) begin
944	`ifdef MODELSIM
945	$display("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
946	`else
947	$error("L2_TAG_ERR"," index error %h ", index_d1[9:0]);
948	`endif
949	end
950	//----- PURELY FOR VERIFICATION -----------------------
951	`endif
952
953	// !!! When Tag is in write or no-op cycles, all output will be "0" since SAs are precharged !!!
954
955	temp_tag_way0 = 0;
956	temp_tag_way1 = 0;
957
958	case(way_d1)
959	2'b01 : begin
960	way0[index_d1] = ~wd_b_l;
961	end
962	2'b10 : begin
963	way1[index_d1] = ~wd_b_l;
964	end
965
966	default: ;
967	endcase
968	end
969	end
970
971
972
973
974
975
976
977
978
979
980
981
982	endmodule
983
984

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