1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: bw_r_rf32x152b.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | //////////////////////////////////////////////////////////////////////// |
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22 | /* |
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23 | // Description: DCache Fill Queue of Load Store Unit. |
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24 | // - Contains invalidates and loads. |
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25 | // - loads will bypass and/or fill dcache. |
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26 | // - Entry at head of queue may have to |
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27 | // be held for multiple passes. |
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28 | // |
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29 | */ |
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30 | |
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31 | //////////////////////////////////////////////////////////////////////// |
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32 | // Local header file includes / local defines |
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33 | //////////////////////////////////////////////////////////////////////// |
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34 | |
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35 | //FPGA_SYN enables all FPGA related modifications |
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36 | `ifdef FPGA_SYN |
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37 | `define FPGA_SYN_32x152 |
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38 | `endif |
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39 | |
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40 | `ifdef FPGA_SYN_32x152 |
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41 | |
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42 | |
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43 | module bw_r_rf32x152b(dout, so, rd_en, rd_adr, wr_en, wr_adr, din, si, se, |
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44 | sehold, rclk, rst_tri_en, reset_l); |
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45 | |
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46 | parameter NUMENTRIES = 32; |
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47 | |
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48 | input [4:0] rd_adr; |
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49 | input rd_en; |
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50 | input wr_en; |
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51 | input [4:0] wr_adr; |
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52 | input [151:0] din; |
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53 | input rclk; |
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54 | input reset_l; |
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55 | input rst_tri_en; |
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56 | input sehold; |
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57 | input si; |
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58 | input se; |
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59 | output [151:0] dout; |
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60 | reg [151:0] dout; |
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61 | output so; |
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62 | |
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63 | wire clk; |
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64 | wire wr_vld; |
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65 | |
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66 | reg [151:0] dfq_mem[(NUMENTRIES - 1):0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ; |
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67 | |
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68 | assign clk = rclk; |
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69 | assign wr_vld = ((wr_en & (~rst_tri_en)) & reset_l); |
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70 | |
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71 | always @(posedge clk) begin |
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72 | if (wr_vld) begin |
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73 | dfq_mem[wr_adr] = din; |
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74 | end |
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75 | end |
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76 | always @(posedge clk) begin |
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77 | if (rd_en) begin |
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78 | dout[151:0] <= dfq_mem[rd_adr[4:0]]; |
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79 | end |
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80 | end |
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81 | endmodule |
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82 | |
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83 | |
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84 | `else |
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85 | |
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86 | module bw_r_rf32x152b (/*AUTOARG*/ |
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87 | // Outputs |
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88 | dout, so, |
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89 | // Inputs |
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90 | rd_en, rd_adr, wr_en, wr_adr, din, |
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91 | si, se, sehold, rclk, rst_tri_en, reset_l); |
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92 | |
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93 | parameter NUMENTRIES = 32 ; // number of entries in dfq |
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94 | |
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95 | input [4:0] rd_adr; // read adr. |
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96 | input rd_en; // read pointer |
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97 | input wr_en; // write pointer vld |
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98 | input [4:0] wr_adr; // write adr. |
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99 | input [151:0] din; // wr data |
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100 | input rclk; // clock |
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101 | input reset_l; // active low reset |
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102 | input rst_tri_en; // reset and scan |
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103 | input sehold; // scan hold |
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104 | input si; // scan in |
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105 | input se; // scan enable |
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106 | |
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107 | output [151:0] dout ; // data read out |
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108 | output so ; // scan out |
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109 | |
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110 | wire [151:0] dout; |
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111 | wire clk; |
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112 | wire wr_vld; |
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113 | |
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114 | reg [151:0] dfq_mem [NUMENTRIES-1:0]; |
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115 | |
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116 | reg [151:0] local_dout; |
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117 | // reg so; |
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118 | |
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119 | integer i,j; |
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120 | |
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121 | // |
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122 | // added for atpg support |
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123 | wire [4:0] sehold_rd_adr; // output of sehold mux - read adr. |
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124 | wire sehold_rd_en; // output of sehold mux - read pointer |
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125 | wire sehold_wr_en; // output of sehold mux - write pointer vld |
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126 | wire [4:0] sehold_wr_adr; // output of sehold mux - write adr. |
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127 | wire [151:0] sehold_din; // wr data |
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128 | |
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129 | wire [4:0] rd_adr_d1; // flopped read adr. |
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130 | wire rd_en_d1; // flopped read pointer |
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131 | wire wr_en_d1; // flopped write pointer vld |
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132 | wire [4:0] wr_adr_d1; // flopped write adr. |
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133 | wire [151:0] din_d1; // flopped wr data |
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134 | |
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135 | // |
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136 | // creating local clock |
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137 | assign clk=rclk; |
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138 | // |
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139 | //========================================================================================= |
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140 | // support for atpg pattern generation |
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141 | //========================================================================================= |
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142 | // |
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143 | // read controls |
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144 | dp_mux2es #(6) mux_sehold_rd_ctrl ( |
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145 | .in0 ({rd_adr[4:0], rd_en}), |
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146 | .in1 ({rd_adr_d1[4:0], rd_en_d1}), |
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147 | .sel (sehold), |
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148 | .dout ({sehold_rd_adr[4:0],sehold_rd_en}) |
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149 | ); |
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150 | |
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151 | dff_s #(6) dff_rd_ctrl_d1( |
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152 | .din ({sehold_rd_adr[4:0], sehold_rd_en}), |
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153 | .q ({rd_adr_d1[4:0], rd_en_d1}), |
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154 | .clk (clk), |
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155 | .se (se), |
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156 | .si (), |
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157 | .so () |
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158 | ); |
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159 | // |
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160 | // write controls |
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161 | dp_mux2es #(6) mux_sehold_wr_ctrl ( |
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162 | .in0 ({wr_adr[4:0], wr_en}), |
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163 | .in1 ({wr_adr_d1[4:0], wr_en_d1}), |
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164 | .sel (sehold), |
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165 | .dout ({sehold_wr_adr[4:0],sehold_wr_en}) |
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166 | ); |
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167 | |
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168 | dff_s #(6) dff_wr_ctrl_d1( |
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169 | .din ({sehold_wr_adr[4:0], sehold_wr_en}), |
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170 | .q ({wr_adr_d1[4:0], wr_en_d1}), |
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171 | .clk (clk), |
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172 | .se (se), |
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173 | .si (), |
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174 | .so () |
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175 | ); |
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176 | // |
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177 | // write data |
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178 | dp_mux2es #(152) mux_sehold_din ( |
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179 | .in0 (din[151:0]), |
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180 | .in1 (din_d1[151:0]), |
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181 | .sel (sehold), |
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182 | .dout (sehold_din[151:0]) |
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183 | ); |
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184 | |
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185 | dff_s #(152) dff_din_d1( |
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186 | .din (sehold_din[151:0]), |
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187 | .q (din_d1[151:0]), |
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188 | .clk (clk), |
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189 | .se (se), |
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190 | .si (), |
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191 | .so () |
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192 | ); |
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193 | |
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194 | // |
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195 | // diable write to register file during reset or scan |
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196 | assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l; |
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197 | |
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198 | // always @ (posedge clk) |
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199 | // begin |
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200 | // so <= 1'bx; |
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201 | // end |
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202 | |
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203 | //========================================================================================= |
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204 | // generate wordlines |
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205 | //========================================================================================= |
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206 | |
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207 | // Word-Line Generation skipped. Implicit in read and write. |
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208 | |
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209 | //========================================================================================= |
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210 | // write or read to/from memory |
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211 | //========================================================================================= |
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212 | |
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213 | |
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214 | always @ ( posedge clk ) |
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215 | begin |
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216 | if (wr_vld) |
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217 | dfq_mem[sehold_wr_adr] = sehold_din[151:0] ; |
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218 | end |
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219 | |
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220 | always @ ( posedge clk ) |
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221 | begin |
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222 | if (sehold_rd_en) |
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223 | begin |
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224 | if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) ) |
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225 | local_dout[151:0] <= 152'hx; |
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226 | else |
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227 | for (j=0;j<NUMENTRIES;j=j+1) |
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228 | begin |
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229 | if (sehold_rd_adr[4:0] == j) |
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230 | local_dout[151:0] <= dfq_mem[j] ; |
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231 | end |
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232 | end |
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233 | end |
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234 | |
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235 | always @ ( ~reset_l ) |
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236 | begin |
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237 | local_dout[151:0] <= |
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238 | 152'hxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx ; |
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239 | end |
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240 | |
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241 | |
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242 | assign dout[151:0] = local_dout[151:0]; |
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243 | |
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244 | // Error Checking : Termination Conditions |
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245 | |
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246 | always @ (posedge clk) |
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247 | begin |
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248 | if ((rd_en == 1'bx) | // wr is undefined, thus terminate |
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249 | (sehold_rd_en & (sehold_rd_adr[4:0] == 5'hxx)) & reset_l) // check outside reset. |
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250 | if (sehold_rd_adr[4:0] == 5'hxx) |
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251 | begin |
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252 | `ifdef INNO_MUXEX |
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253 | `else |
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254 | `ifdef DEFINE_0IN |
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255 | // 0in <fire -message "rf32x152b_error, read pointer error (X)" |
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256 | $display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]); |
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257 | `else |
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258 | `ifdef MODELSIM |
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259 | $display("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]); |
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260 | `else |
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261 | $error("rf32x152b_error"," read pointer error (X) %h ", rd_adr[4:0]); |
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262 | `endif |
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263 | `endif |
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264 | `endif |
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265 | end |
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266 | if ((wr_vld == 1'bx) | // wr is undefined, thus terminate |
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267 | (wr_vld & (sehold_wr_adr[4:0] == 5'hxx)) & reset_l) // check outside reset. |
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268 | begin |
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269 | `ifdef INNO_MUXEX |
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270 | `else |
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271 | `ifdef DEFINE_0IN |
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272 | // 0in <fire -message "rf32x152b_error, write error (X)" |
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273 | $display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]); |
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274 | `else |
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275 | `ifdef MODELSIM |
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276 | $display("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]); |
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277 | `else |
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278 | $error("rf32x152b_error"," write error (X) %h ", wr_adr[4:0]); |
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279 | `endif |
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280 | `endif |
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281 | `endif |
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282 | end |
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283 | end |
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284 | |
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285 | endmodule |
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286 | |
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287 | `endif |
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288 | |
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