source: XOpenSparcT1/trunk/Xilinx/dram_fifo.v @ 6

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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file dram_fifo.v when simulating
// the core, dram_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module dram_fifo(
        rst,
        wr_clk,
        rd_clk,
        din,
        wr_en,
        rd_en,
        dout,
        full,
        empty,
        wr_data_count);


input rst;
input wr_clk;
input rd_clk;
input [103 : 0] din;
input wr_en;
input rd_en;
output [103 : 0] dout;
output full;
output empty;
output [7 : 0] wr_data_count;

// synthesis translate_off

      FIFO_GENERATOR_V6_2 #(
                .C_COMMON_CLOCK(0),
                .C_COUNT_TYPE(0),
                .C_DATA_COUNT_WIDTH(10),
                .C_DEFAULT_VALUE("BlankString"),
                .C_DIN_WIDTH(104),
                .C_DOUT_RST_VAL("0"),
                .C_DOUT_WIDTH(104),
                .C_ENABLE_RLOCS(0),
                .C_ENABLE_RST_SYNC(1),
                .C_ERROR_INJECTION_TYPE(0),
                .C_FAMILY("virtex5"),
                .C_FULL_FLAGS_RST_VAL(1),
                .C_HAS_ALMOST_EMPTY(0),
                .C_HAS_ALMOST_FULL(0),
                .C_HAS_BACKUP(0),
                .C_HAS_DATA_COUNT(0),
                .C_HAS_INT_CLK(0),
                .C_HAS_MEMINIT_FILE(0),
                .C_HAS_OVERFLOW(0),
                .C_HAS_RD_DATA_COUNT(0),
                .C_HAS_RD_RST(0),
                .C_HAS_RST(1),
                .C_HAS_SRST(0),
                .C_HAS_UNDERFLOW(0),
                .C_HAS_VALID(0),
                .C_HAS_WR_ACK(0),
                .C_HAS_WR_DATA_COUNT(1),
                .C_HAS_WR_RST(0),
                .C_IMPLEMENTATION_TYPE(2),
                .C_INIT_WR_PNTR_VAL(0),
                .C_MEMORY_TYPE(1),
                .C_MIF_FILE_NAME("BlankString"),
                .C_MSGON_VAL(1),
                .C_OPTIMIZATION_MODE(0),
                .C_OVERFLOW_LOW(0),
                .C_PRELOAD_LATENCY(1),
                .C_PRELOAD_REGS(0),
                .C_PRIM_FIFO_TYPE("1kx36"),
                .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
                .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
                .C_PROG_EMPTY_TYPE(0),
                .C_PROG_FULL_THRESH_ASSERT_VAL(1021),
                .C_PROG_FULL_THRESH_NEGATE_VAL(1020),
                .C_PROG_FULL_TYPE(0),
                .C_RD_DATA_COUNT_WIDTH(10),
                .C_RD_DEPTH(1024),
                .C_RD_FREQ(1),
                .C_RD_PNTR_WIDTH(10),
                .C_UNDERFLOW_LOW(0),
                .C_USE_DOUT_RST(1),
                .C_USE_ECC(0),
                .C_USE_EMBEDDED_REG(0),
                .C_USE_FIFO16_FLAGS(0),
                .C_USE_FWFT_DATA_COUNT(0),
                .C_VALID_LOW(0),
                .C_WR_ACK_LOW(0),
                .C_WR_DATA_COUNT_WIDTH(8),
                .C_WR_DEPTH(1024),
                .C_WR_FREQ(1),
                .C_WR_PNTR_WIDTH(10),
                .C_WR_RESPONSE_LATENCY(1))
        inst (
                .RST(rst),
                .WR_CLK(wr_clk),
                .RD_CLK(rd_clk),
                .DIN(din),
                .WR_EN(wr_en),
                .RD_EN(rd_en),
                .DOUT(dout),
                .FULL(full),
                .EMPTY(empty),
                .WR_DATA_COUNT(wr_data_count),
                .BACKUP(),
                .BACKUP_MARKER(),
                .CLK(),
                .SRST(),
                .WR_RST(),
                .RD_RST(),
                .PROG_EMPTY_THRESH(),
                .PROG_EMPTY_THRESH_ASSERT(),
                .PROG_EMPTY_THRESH_NEGATE(),
                .PROG_FULL_THRESH(),
                .PROG_FULL_THRESH_ASSERT(),
                .PROG_FULL_THRESH_NEGATE(),
                .INT_CLK(),
                .INJECTDBITERR(),
                .INJECTSBITERR(),
                .ALMOST_FULL(),
                .WR_ACK(),
                .OVERFLOW(),
                .ALMOST_EMPTY(),
                .VALID(),
                .UNDERFLOW(),
                .DATA_COUNT(),
                .RD_DATA_COUNT(),
                .PROG_FULL(),
                .PROG_EMPTY(),
                .SBITERR(),
                .DBITERR());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of dram_fifo is "black_box"

endmodule