| 1 | ############################################################## |
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| 2 | # |
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| 3 | # Xilinx Core Generator version 12.3 |
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| 4 | # Date: Thu Mar 31 13:52:40 2011 |
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| 5 | # |
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| 6 | ############################################################## |
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| 7 | # |
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| 8 | # This file contains the customisation parameters for a |
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| 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended |
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| 10 | # that you do not manually alter this file as it may cause |
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| 11 | # unexpected and unsupported behavior. |
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| 12 | # |
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| 13 | ############################################################## |
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| 14 | # |
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| 15 | # BEGIN Project Options |
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| 16 | SET addpads = false |
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| 17 | SET asysymbol = false |
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| 18 | SET busformat = BusFormatAngleBracketNotRipped |
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| 19 | SET createndf = false |
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| 20 | SET designentry = Verilog |
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| 21 | SET device = xc5vlx110t |
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| 22 | SET devicefamily = virtex5 |
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| 23 | SET flowvendor = Other |
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| 24 | SET formalverification = false |
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| 25 | SET foundationsym = false |
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| 26 | SET implementationfiletype = Ngc |
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| 27 | SET package = ff1738 |
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| 28 | SET removerpms = false |
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| 29 | SET simulationfiles = Behavioral |
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| 30 | SET speedgrade = -2 |
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| 31 | SET verilogsim = true |
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| 32 | SET vhdlsim = false |
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| 33 | # END Project Options |
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| 34 | # BEGIN Select |
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| 35 | SELECT Fifo_Generator family Xilinx,_Inc. 6.2 |
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| 36 | # END Select |
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| 37 | # BEGIN Parameters |
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| 38 | CSET almost_empty_flag=false |
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| 39 | CSET almost_full_flag=false |
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| 40 | CSET component_name=dram_fifo_fall |
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| 41 | CSET data_count=false |
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| 42 | CSET data_count_width=10 |
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| 43 | CSET disable_timing_violations=false |
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| 44 | CSET dout_reset_value=0 |
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| 45 | CSET empty_threshold_assert_value=4 |
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| 46 | CSET empty_threshold_negate_value=5 |
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| 47 | CSET enable_ecc=false |
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| 48 | CSET enable_int_clk=false |
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| 49 | CSET enable_reset_synchronization=true |
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| 50 | CSET fifo_implementation=Independent_Clocks_Block_RAM |
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| 51 | CSET full_flags_reset_value=1 |
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| 52 | CSET full_threshold_assert_value=1023 |
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| 53 | CSET full_threshold_negate_value=1022 |
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| 54 | CSET inject_dbit_error=false |
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| 55 | CSET inject_sbit_error=false |
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| 56 | CSET input_data_width=104 |
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| 57 | CSET input_depth=1024 |
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| 58 | CSET output_data_width=104 |
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| 59 | CSET output_depth=1024 |
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| 60 | CSET overflow_flag=false |
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| 61 | CSET overflow_sense=Active_High |
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| 62 | CSET performance_options=First_Word_Fall_Through |
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| 63 | CSET programmable_empty_type=No_Programmable_Empty_Threshold |
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| 64 | CSET programmable_full_type=No_Programmable_Full_Threshold |
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| 65 | CSET read_clock_frequency=1 |
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| 66 | CSET read_data_count=false |
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| 67 | CSET read_data_count_width=10 |
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| 68 | CSET reset_pin=true |
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| 69 | CSET reset_type=Asynchronous_Reset |
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| 70 | CSET underflow_flag=false |
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| 71 | CSET underflow_sense=Active_High |
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| 72 | CSET use_dout_reset=true |
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| 73 | CSET use_embedded_registers=false |
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| 74 | CSET use_extra_logic=false |
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| 75 | CSET valid_flag=false |
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| 76 | CSET valid_sense=Active_High |
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| 77 | CSET write_acknowledge_flag=false |
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| 78 | CSET write_acknowledge_sense=Active_High |
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| 79 | CSET write_clock_frequency=1 |
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| 80 | CSET write_data_count=true |
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| 81 | CSET write_data_count_width=8 |
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| 82 | # END Parameters |
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| 83 | GENERATE |
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| 84 | # CRC: 96af05d3 |
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