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source: XOpenSparcT1/trunk/os2wb/os2wb_dual.v @ 6

Revision 6, 49.3 KB checked in by pntsvt00, 14 years ago (diff)
versione iniziale opensparc

Rev	Line
[6]	1	`timescale 1ns / 1ps
	2	//////////////////////////////////////////////////////////////////////////////////
	3	// Company: (C) Athree, 2009
	4	// Engineer: Dmitry Rozhdestvenskiy
	5	// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
	6	//
	7	// Design Name: Bridge from SPARC Core to Wishbone Master
	8	// Module Name: os2wb
	9	// Project Name: SPARC SoC single-core
	10	//
	11	// LICENSE:
	12	// This is a Free Hardware Design; you can redistribute it and/or
	13	// modify it under the terms of the GNU General Public License
	14	// version 2 as published by the Free Software Foundation.
	15	// The above named program is distributed in the hope that it will
	16	// be useful, but WITHOUT ANY WARRANTY; without even the implied
	17	// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	18	// See the GNU General Public License for more details.
	19	//
	20	//////////////////////////////////////////////////////////////////////////////////
	21	module os2wb_dual(
	22	input clk,
	23	input rstn,
	24
	25	// Core interface
	26	input [ 4:0] pcx_req,
	27	input pcx_atom,
	28	input [123:0] pcx_data,
	29	output reg [ 4:0] pcx_grant,
	30	output reg cpx_ready,
	31	output reg [144:0] cpx_packet,
	32
	33	// Core 2nd interface
	34	input [ 4:0] pcx1_req,
	35	input pcx1_atom,
	36	input [123:0] pcx1_data,
	37	output reg [ 4:0] pcx1_grant,
	38	output reg cpx1_ready,
	39	output reg [144:0] cpx1_packet,
	40
	41	// Wishbone master interface
	42	input [ 63:0] wb_data_i,
	43	input wb_ack,
	44	output reg wb_cycle,
	45	output reg wb_strobe,
	46	output reg wb_we,
	47	output reg [ 7:0] wb_sel,
	48	output reg [ 63:0] wb_addr,
	49	output reg [ 63:0] wb_data_o,
	50
	51	// FPU interface
	52	output reg [123:0] fp_pcx,
	53	output reg fp_req,
	54	input [144:0] fp_cpx,
	55	input fp_rdy,
	56
	57	// Ethernet interrupt, sensed on posedge, mapped to vector 'd29
	58	input eth_int
	59	);
	60
	61	reg [123:0] pcx_packet_d; // Latched incoming PCX packet
	62	reg [123:0] pcx_packet_2nd; // Second packet for atomic (CAS)
	63	reg [ 4:0] pcx_req_d; // Latched request
	64	reg pcx_atom_d; // Latched atomic flasg
	65	reg [ 4:0] state; // FSM state
	66	reg [144:0] cpx_packet_1; // First CPX packet
	67	reg [144:0] cpx_packet_2; // Second CPX packet (for atomics and cached IFILLs)
	68	reg cpx_two_packet; // CPX answer is two-packet (!=atomic, SWAP has atomic==0 and answer is two-packet)
	69
	70	wire [111:0] inval_vect0; // Invalidate, instr/data, way
	71	wire [111:0] inval_vect1; // IFill may cause two D lines invalidation at a time
	72
	73	wire [1:0] othercachehit;
	74	wire [1:0] othercpuhit;
	75	wire [1:0] wayval0;
	76	wire [1:0] wayval1;
	77
	78	`define TEST_DRAM_1 5'b00000
	79	`define TEST_DRAM_2 5'b00001
	80	`define TEST_DRAM_3 5'b00010
	81	`define TEST_DRAM_4 5'b00011
	82	`define INIT_DRAM_1 5'b00100
	83	`define INIT_DRAM_2 5'b00101
	84	`define WAKEUP 5'b00110
	85	`define PCX_IDLE 5'b00111
	86	`define GOT_PCX_REQ 5'b01000
	87	`define PCX_REQ_2ND 5'b01001
	88	`define PCX_REQ_STEP1 5'b01010
	89	`define PCX_REQ_STEP1_1 5'b01011
	90	`define PCX_REQ_STEP2 5'b01100
	91	`define PCX_REQ_STEP2_1 5'b01101
	92	`define PCX_REQ_STEP3 5'b01110
	93	`define PCX_REQ_STEP3_1 5'b01111
	94	`define PCX_REQ_STEP4 5'b10000
	95	`define PCX_REQ_STEP4_1 5'b10001
	96	`define PCX_BIS 5'b10010
	97	`define PCX_BIS_1 5'b10011
	98	`define PCX_BIS_2 5'b10100
	99	`define CPX_READY_1 5'b10101
	100	`define CPX_READY_2 5'b10110
	101	`define PCX_REQ_STEP1_2 5'b10111
	102	`define PCX_UNKNOWN 5'b11000
	103	`define PCX_FP_1 5'b11001
	104	`define PCX_FP_2 5'b11010
	105	`define FP_WAIT 5'b11011
	106	`define CPX_FP 5'b11100
	107	`define CPX_SEND_ETH_IRQ 5'b11101
	108	`define CPX_INT_VEC_DIS 5'b11110
	109	`define PCX_REQ_CAS_COMPARE 5'b11111
	110
	111	`define MEM_SIZE 64'h00000000_10000000
	112
	113	`define TEST_DRAM 1
	114	`define DEBUGGING 1
	115
	116	reg cache_init;
	117	wire [3:0] dcache0_hit;
	118	wire [3:0] dcache1_hit;
	119	wire [3:0] icache_hit;
	120	reg multi_hit;
	121	reg multi_hit1;
	122	reg eth_int_d;
	123	reg eth_int_send;
	124	reg eth_int_sent;
	125	reg [3:0] cnt;
	126
	127	// PCX channel FIFO
	128	wire [129:0] pcx_data_fifo;
	129	wire pcx_fifo_empty;
	130	reg [ 4:0] pcx_req_1;
	131	reg [ 4:0] pcx_req_2;
	132	reg pcx_atom_1;
	133	reg pcx_atom_2;
	134	reg pcx_data_123_d;
	135
	136	// PCX 2nf channel FIFO
	137	wire [129:0] pcx1_data_fifo;
	138	wire pcx1_fifo_empty;
	139	reg [ 4:0] pcx1_req_1;
	140	reg [ 4:0] pcx1_req_2;
	141	reg pcx1_atom_1;
	142	reg pcx1_atom_2;
	143	reg pcx1_data_123_d;
	144
	145	reg fifo_rd;
	146	reg fifo_rd1;
	147
	148	always @(posedge clk)
	149	begin
	150	pcx_req_1<=pcx_req;
	151	pcx_atom_1<=pcx_atom;
	152	pcx_atom_2<=pcx_atom_1;
	153	pcx_req_2<=pcx_atom_1 ? pcx_req_1:5'b0;
	154	pcx_grant<=(pcx_req_1 \| pcx_req_2);
	155	pcx_data_123_d<=pcx_data[123];
	156
	157	pcx1_req_1<=pcx1_req;
	158	pcx1_atom_1<=pcx1_atom;
	159	pcx1_atom_2<=pcx1_atom_1;
	160	pcx1_req_2<=pcx1_atom_1 ? pcx1_req_1:5'b0;
	161	pcx1_grant<=(pcx1_req_1 \| pcx1_req_2);
	162	pcx1_data_123_d<=pcx1_data[123];
	163	end
	164
	165	/*pcx_fifo pcx_fifo_inst(
	166	// FIFO should be first word fall-through
	167	// It has no full flag as the core will send only limited number of requests,
	168	// in original design we used it 32 words deep
	169	// Just make it deeper if you experience overflow -
	170	// you can't just send no grant on full because the core expects immediate
	171	// grant for at least two requests for each zone
	172	.aclr(!rstn),
	173	.clock(clk),
	174	.data({pcx_atom_1,pcx_req_1,pcx_data}),
	175	.rdreq(fifo_rd),
	176	.wrreq((pcx_req_1!=5'b00000 && pcx_data[123]) \|\| (pcx_atom_2 && pcx_data_123_d)),
	177	// Second atomic packet for FPU may be invalid, but should be sent to FPU
	178	// so if the first atomic packet is valid we latch both
	179	.empty(pcx_fifo_empty),
	180	.q(pcx_data_fifo)
	181	);
	182	*/
	183	pcx_fifo pcx_fifo_inst(
	184	.clk(clk),
	185	.rst(!rstn),
	186	.din({pcx_atom_1,pcx_req_1,pcx_data}),
	187	.rd_en(fifo_rd),
	188	.wr_en((pcx_req_1!=5'b00000 && pcx_data[123]) \|\| (pcx_atom_2 && pcx_data_123_d)),
	189	.empty(pcx_fifo_empty),
	190	.dout(pcx_data_fifo)
	191	);
	192
	193
	194	pcx_fifo pcx_fifo_inst1(
	195	.clk(clk),
	196	.rst(!rstn),
	197	.din({pcx1_atom_1,pcx1_req_1,pcx1_data}),
	198	.rd_en(fifo_rd1),
	199	.wr_en((pcx1_req_1!=5'b00000 && pcx1_data[123]) \|\| (pcx1_atom_2 && pcx1_data_123_d)),
	200	.empty(pcx1_fifo_empty),
	201	.dout(pcx1_data_fifo)
	202	);
	203	// --------------------------
	204
	205	reg wb_ack_d;
	206
	207	always @(posedge clk or negedge rstn)
	208	begin
	209	if(!rstn)
	210	eth_int_send<=0;
	211	else
	212	begin
	213	wb_ack_d<=wb_ack;
	214	eth_int_d<=eth_int;
	215	if(eth_int && !eth_int_d)
	216	eth_int_send<=1;
	217	else
	218	if(eth_int_sent)
	219	eth_int_send<=0;
	220	end
	221	end
	222	wire [123:0] pcx_packet;
	223	reg cpu;
	224	assign pcx_packet=cpu ? pcx1_data_fifo[123:0]:pcx_data_fifo[123:0];
	225	reg cpu2;
	226
	227	always @(posedge clk or negedge rstn)
	228	if(rstn==0)
	229	begin
	230	if(`TEST_DRAM)
	231	state<=`TEST_DRAM_1;
	232	else
	233	state<=`INIT_DRAM_1; // DRAM initialization is mandatory!
	234	cpx_ready<=0;
	235	fifo_rd<=0;
	236	cpx_packet<=145'b0;
	237	wb_cycle<=0;
	238	wb_strobe<=0;
	239	wb_we<=0;
	240	wb_sel<=0;
	241	wb_addr<=64'b0;
	242	wb_data_o<=64'b0;
	243	pcx_packet_d<=124'b0;
	244	fp_pcx<=124'b0;
	245	fp_req<=0;
	246	end
	247	else
	248	case(state)
	249	`TEST_DRAM_1:
	250	begin
	251	wb_cycle<=1;
	252	wb_strobe<=1;
	253	wb_sel<=8'hFF;
	254	wb_we<=1;
	255	state<=`TEST_DRAM_2;
	256	end
	257	`TEST_DRAM_2:
	258	if(wb_ack)
	259	begin
	260	wb_strobe<=0;
	261	if(wb_addr<`MEM_SIZE-8)
	262	begin
	263	wb_addr[31:0]<=wb_addr[31:0]+8;
	264	wb_data_o<={wb_addr[31:0]+8,wb_addr[31:0]+8};
	265	state<=`TEST_DRAM_1;
	266	end
	267	else
	268	begin
	269	state<=`TEST_DRAM_3;
	270	wb_cycle<=0;
	271	wb_sel<=0;
	272	wb_we<=0;
	273	wb_data_o<=64'b0;
	274	wb_addr<=64'b0;
	275	end
	276	end
	277	`TEST_DRAM_3:
	278	begin
	279	wb_cycle<=1;
	280	wb_strobe<=1;
	281	wb_sel<=8'hFF;
	282	state<=`TEST_DRAM_4;
	283	end
	284	`TEST_DRAM_4:
	285	if(wb_ack)
	286	begin
	287	wb_strobe<=0;
	288	if(wb_addr<`MEM_SIZE-8)
	289	begin
	290	if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]})
	291	begin
	292	wb_addr[31:0]<=wb_addr[31:0]+8;
	293	state<=`TEST_DRAM_3;
	294	end
	295	end
	296	else
	297	begin
	298	state<=`INIT_DRAM_1;
	299	wb_cycle<=0;
	300	wb_sel<=0;
	301	wb_we<=0;
	302	wb_data_o<=64'b0;
	303	wb_addr<=64'b0;
	304	end
	305	end
	306	`INIT_DRAM_1:
	307	begin
	308	wb_cycle<=1;
	309	wb_strobe<=1;
	310	wb_sel<=8'hFF;
	311	wb_we<=1;
	312	cache_init<=1; // We also init cache directories here
	313	state<=`INIT_DRAM_2;
	314	end
	315	`INIT_DRAM_2:
	316	if(wb_ack)
	317	begin
	318	wb_strobe<=0;
	319	if(wb_addr<`MEM_SIZE-8)
	320	begin
	321	wb_addr[31:0]<=wb_addr[31:0]+8;
	322	pcx_packet_d[64+11:64+4]<=pcx_packet_d[64+11:64+4]+1; // Address for cachedir init
	323	state<=`INIT_DRAM_1;
	324	end
	325	else
	326	begin
	327	state<=`WAKEUP;
	328	wb_cycle<=0;
	329	wb_sel<=0;
	330	wb_we<=0;
	331	cache_init<=0;
	332	wb_addr<=64'b0;
	333	end
	334	end
	335	`WAKEUP:
	336	begin
	337	cpx_packet<=145'h1700000000000000000000000000000010001;
	338	cpx_ready<=1;
	339	state<=`PCX_IDLE;
	340	end
	341	`PCX_IDLE:
	342	begin
	343	cnt<=0;
	344	cpx_packet<=145'b0;
	345	cpx_ready<=0;
	346	cpx1_packet<=145'b0;
	347	cpx1_ready<=0;
	348	cpx_two_packet<=0;
	349	multi_hit<=0;
	350	multi_hit1<=0;
	351	if(eth_int_send)
	352	begin
	353	state<=`CPX_SEND_ETH_IRQ;
	354	eth_int_sent<=1;
	355	end
	356	else
	357	if(!pcx_fifo_empty)
	358	begin
	359	pcx_req_d<=pcx_data_fifo[128:124];
	360	pcx_atom_d<=pcx_data_fifo[129];
	361	fifo_rd<=1;
	362	state<=`GOT_PCX_REQ;
	363	cpu<=0;
	364	cpu2<=0;
	365	end
	366	else
	367	if(!pcx1_fifo_empty)
	368	begin
	369	pcx_req_d<=pcx1_data_fifo[128:124];
	370	pcx_atom_d<=pcx1_data_fifo[129];
	371	fifo_rd1<=1;
	372	state<=`GOT_PCX_REQ;
	373	cpu<=1;
	374	cpu2<=1;
	375	end
	376	end
	377	`GOT_PCX_REQ:
	378	begin
	379	pcx_packet_d<=pcx_packet;
	380	if(`DEBUGGING)
	381	begin
	382	wb_sel[1:0]<=pcx_packet[113:112];
	383	wb_sel[2]<=1;
	384	end
	385	if(pcx_packet[103:64]==40'h9800000800 && pcx_packet[122:118]==5'b00001)
	386	begin
	387	state<=`CPX_INT_VEC_DIS;
	388	fifo_rd<=0;
	389	fifo_rd1<=0;
	390	end
	391	else
	392	if(pcx_atom_d==0)
	393	begin
	394	fifo_rd<=0;
	395	fifo_rd1<=0;
	396	if(pcx_packet[122:118]==5'b01010) // FP req
	397	begin
	398	state<=`PCX_FP_1;
	399	pcx_packet_2nd[123]<=0;
	400	end
	401	else
	402	state<=`PCX_REQ_STEP1;
	403	end
	404	else
	405	state<=`PCX_REQ_2ND;
	406	end
	407	`PCX_REQ_2ND:
	408	begin
	409	pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics
	410	if(`DEBUGGING)
	411	if(pcx_fifo_empty)
	412	wb_sel<=8'h67;
	413	fifo_rd<=0;
	414	fifo_rd1<=0;
	415	if(pcx_packet_d[122:118]==5'b01010) // FP req
	416	state<=`PCX_FP_1;
	417	else
	418	state<=`PCX_REQ_STEP1;
	419	end
	420	`PCX_REQ_STEP1:
	421	begin
	422	if(pcx_packet_d[111]==1'b1) // Invalidate request
	423	begin
	424	cpx_packet_1[144]<=1; // Valid
	425	cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK
	426	cpx_packet_1[139]<=1; // L2 miss
	427	cpx_packet_1[138:137]<=0; // Error
	428	cpx_packet_1[136]<=pcx_packet_d[117]; // Non-cacheble
	429	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	430	cpx_packet_1[133:131]<=0; // Way valid
	431	cpx_packet_1[130]<=((pcx_packet_d[122:118]==5'b10000) && (pcx_req_d==5'b10000)) ? 1:0; // Four byte fill
	432	cpx_packet_1[129]<=pcx_atom_d;
	433	cpx_packet_1[128]<=pcx_packet_d[110]; // Prefetch
	434	cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/BIS/,pcx_packet_d[122:118]==5'b00000 ? 2'b01:2'b10,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],112'b0};
	435	state<=`CPX_READY_1;
	436	end
	437	else
	438	if(pcx_packet_d[122:118]!=5'b01001) // Not INT
	439	begin
	440	wb_cycle<=1'b1;
	441	wb_strobe<=1'b1;
	442	if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) \|\| pcx_packet_d[122:118]==5'b00010 \|\| pcx_packet_d[122:118]==5'b00100 \|\| pcx_packet_d[122:118]==5'b00110)
	443	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first
	444	else
	445	if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4])
	446	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill
	447	else
	448	if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8
	449	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000};
	450	else
	451	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3],3'b000};
	452	wb_data_o<=pcx_packet_d[63:0];
	453	state<=`PCX_REQ_STEP1_1;
	454	end
	455	else
	456	//if((pcx_packet_d[12:10]!=3'b000) && !pcx_packet_d[117]) // Not FLUSH int and not this core
	457	// state<=`PCX_IDLE;
	458	//else
	459	state<=`CPX_READY_1;
	460	case(pcx_packet_d[122:118]) // Packet type
	461	5'b00000://Load
	462	begin
	463	wb_we<=0;
	464	if(!pcx_req_d[4])
	465	wb_sel<=8'b11111111; // DRAM requests are always 128 bit
	466	else
	467	case(pcx_packet_d[106:104]) //Size
	468	3'b000://Byte
	469	case(pcx_packet_d[64+2:64])
	470	3'b000:wb_sel<=8'b10000000;
	471	3'b001:wb_sel<=8'b01000000;
	472	3'b010:wb_sel<=8'b00100000;
	473	3'b011:wb_sel<=8'b00010000;
	474	3'b100:wb_sel<=8'b00001000;
	475	3'b101:wb_sel<=8'b00000100;
	476	3'b110:wb_sel<=8'b00000010;
	477	3'b111:wb_sel<=8'b00000001;
	478	endcase
	479	3'b001://Halfword
	480	case(pcx_packet_d[64+2:64+1])
	481	2'b00:wb_sel<=8'b11000000;
	482	2'b01:wb_sel<=8'b00110000;
	483	2'b10:wb_sel<=8'b00001100;
	484	2'b11:wb_sel<=8'b00000011;
	485	endcase
	486	3'b010://Word
	487	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	488	3'b011://Doubleword
	489	wb_sel<=8'b11111111;
	490	3'b100://Quadword
	491	wb_sel<=8'b11111111;
	492	3'b111://Cacheline
	493	wb_sel<=8'b11111111;
	494	default:
	495	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	496	endcase
	497	end
	498	5'b00001://Store
	499	begin
	500	wb_we<=1;
	501	if(pcx_packet_d[110:109]!=2'b00) //Block (or init) store
	502	wb_sel<=8'b11111111; // Blocks are always 64 bit
	503	else
	504	case(pcx_packet_d[106:104]) //Size
	505	3'b000://Byte
	506	case(pcx_packet_d[64+2:64])
	507	3'b000:wb_sel<=8'b10000000;
	508	3'b001:wb_sel<=8'b01000000;
	509	3'b010:wb_sel<=8'b00100000;
	510	3'b011:wb_sel<=8'b00010000;
	511	3'b100:wb_sel<=8'b00001000;
	512	3'b101:wb_sel<=8'b00000100;
	513	3'b110:wb_sel<=8'b00000010;
	514	3'b111:wb_sel<=8'b00000001;
	515	endcase
	516	3'b001://Halfword
	517	case(pcx_packet_d[64+2:64+1])
	518	2'b00:wb_sel<=8'b11000000;
	519	2'b01:wb_sel<=8'b00110000;
	520	2'b10:wb_sel<=8'b00001100;
	521	2'b11:wb_sel<=8'b00000011;
	522	endcase
	523	3'b010://Word
	524	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	525	3'b011://Doubleword
	526	wb_sel<=8'b11111111;
	527	default:
	528	if(`DEBUGGING)
	529	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	530	endcase
	531	end
	532	5'b00010://CAS
	533	begin
	534	wb_we<=0; //Load first
	535	wb_sel<=8'b11111111; // CAS loads are as cacheline
	536	end
	537	5'b00100://STRLOAD
	538	begin
	539	wb_we<=0;
	540	wb_sel<=8'b11111111; // Stream loads are always 128 bit
	541	end
	542	5'b00101://STRSTORE
	543	begin
	544	wb_we<=1;
	545	case(pcx_packet_d[106:104]) //Size
	546	3'b000://Byte
	547	case(pcx_packet_d[64+2:64])
	548	3'b000:wb_sel<=8'b10000000;
	549	3'b001:wb_sel<=8'b01000000;
	550	3'b010:wb_sel<=8'b00100000;
	551	3'b011:wb_sel<=8'b00010000;
	552	3'b100:wb_sel<=8'b00001000;
	553	3'b101:wb_sel<=8'b00000100;
	554	3'b110:wb_sel<=8'b00000010;
	555	3'b111:wb_sel<=8'b00000001;
	556	endcase
	557	3'b001://Halfword
	558	case(pcx_packet_d[64+2:64+1])
	559	2'b00:wb_sel<=8'b11000000;
	560	2'b01:wb_sel<=8'b00110000;
	561	2'b10:wb_sel<=8'b00001100;
	562	2'b11:wb_sel<=8'b00000011;
	563	endcase
	564	3'b010://Word
	565	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	566	3'b011://Doubleword
	567	wb_sel<=8'b11111111;
	568	3'b100://Quadword
	569	wb_sel<=8'b11111111;
	570	3'b111://Cacheline
	571	wb_sel<=8'b11111111;
	572	default:
	573	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	574	endcase
	575	end
	576	5'b00110://SWAP/LDSTUB
	577	begin
	578	wb_we<=0; // Load first, as CAS
	579	wb_sel<=8'b11111111; // SWAP/LDSTUB loads are as cacheline
	580	end
	581	5'b01001://INT
	582	if(pcx_packet_d[117]) // Flush
	583	begin
	584	cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
	585	//cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
	586	//cpx_two_packet<=1;
	587	//cpu2<=!cpu; // Flush should be sent to both cores
	588	end
	589	else // Tread-to-thread interrupt
	590	begin
	591	cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
	592	cpu<=pcx_packet_d[10];
	593	end
	594	//5'b01010: FP1 - processed by separate state
	595	//5'b01011: FP2 - processed by separate state
	596	//5'b01101: FWDREQ - not implemented
	597	//5'b01110: FWDREPL - not implemented
	598	5'b10000://IFILL
	599	begin
	600	wb_we<=0;
	601	if(pcx_req_d[4]) // I/O access
	602	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	603	else
	604	wb_sel<=8'b11111111;
	605	end
	606	default:
	607	begin
	608	wb_we<=0;
	609	wb_sel<=8'b10101010; // Unreal eye-catching value for debug
	610	end
	611	endcase
	612	end
	613	`PCX_REQ_STEP1_1:
	614	state<=`PCX_REQ_STEP1_2; // Delay for L1 directory
	615	`PCX_REQ_STEP1_2:
	616	begin
	617	if(wb_ack \|\| wb_ack_d)
	618	begin
	619	cpx_packet_1[144]<=1; // Valid
	620	cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) \|\| (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill
	621	cpx_packet_1[138:137]<=0; // Error
	622	cpx_packet_1[136]<=pcx_packet_d[117] \|\| (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too
	623	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	624	if((pcx_packet_d[122:118]==5'b00000 && !pcx_packet_d[117] && !pcx_packet_d[110]) \|\| (pcx_packet_d[122:118]==5'b10000)) // Cacheble Load or IFill
	625	cpx_packet_1[133:131]<={othercachehit[0],wayval0};
	626	else
	627	cpx_packet_1[133:131]<=3'b000; // Way valid
	628	if(pcx_packet_d[122:118]==5'b00100) // Strload
	629	cpx_packet_1[130]<=pcx_packet_d[106]; // A
	630	else
	631	if(pcx_packet_d[122:118]==5'b00101) // Stream store
	632	cpx_packet_1[130]<=pcx_packet_d[108]; // A
	633	else
	634	cpx_packet_1[130]<=((pcx_packet_d[122:118]==5'b10000) && pcx_req_d[4]) ? 1:0; // Four byte fill
	635	if(pcx_packet_d[122:118]==5'b00100) // Strload
	636	cpx_packet_1[129]<=pcx_packet_d[105]; // B
	637	else
	638	cpx_packet_1[129]<=pcx_atom_d \|\| (pcx_packet_d[122:118]==5'b00110); // SWAP is single-packet but needs atom in CPX
	639	cpx_packet_1[128]<=pcx_packet_d[110] && pcx_packet_d[122:118]==5'b00000; // Prefetch
	640	cpx_packet_2[144]<=1; // Valid
	641	cpx_packet_2[139]<=0; // L2 miss
	642	cpx_packet_2[138:137]<=0; // Error
	643	cpx_packet_2[136]<=pcx_packet_d[117] \|\| (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too
	644	cpx_packet_2[135:134]<=pcx_packet_d[113:112]; // Thread ID
	645	if(pcx_packet_d[122:118]==5'b10000) // IFill
	646	cpx_packet_2[133:131]<={othercachehit[1],wayval1};
	647	else
	648	cpx_packet_2[133:131]<=3'b000; // Way valid
	649	cpx_packet_2[130]<=0; // Four byte fill
	650	cpx_packet_2[129]<=pcx_atom_d \|\| (pcx_packet_d[122:118]==5'b00110) \|\| ((pcx_packet_d[122:118]==5'b10000) && !pcx_req_d[4]);
	651	cpx_packet_2[128]<=0; // Prefetch
	652	wb_strobe<=0;
	653	wb_sel<=8'b0;
	654	wb_addr<=64'b0;
	655	wb_data_o<=64'b0;
	656	wb_we<=0;
	657	case(pcx_packet_d[122:118]) // Packet type
	658	5'b00000://Load
	659	begin
	660	cpx_packet_1[143:140]<=4'b0000; // Type
	661	if(!pcx_req_d[4])
	662	begin
	663	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	664	state<=`PCX_REQ_STEP2;
	665	end
	666	else
	667	case(pcx_packet_d[106:104]) //Size
	668	3'b000://Byte
	669	begin
	670	case(pcx_packet_d[64+2:64])
	671	3'b000:cpx_packet_1[127:0]<={wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56]};
	672	3'b001:cpx_packet_1[127:0]<={wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48]};
	673	3'b010:cpx_packet_1[127:0]<={wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40]};
	674	3'b011:cpx_packet_1[127:0]<={wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32]};
	675	3'b100:cpx_packet_1[127:0]<={wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24]};
	676	3'b101:cpx_packet_1[127:0]<={wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16]};
	677	3'b110:cpx_packet_1[127:0]<={wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8]};
	678	3'b111:cpx_packet_1[127:0]<={wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0]};
	679	endcase
	680	wb_cycle<=0;
	681	state<=`CPX_READY_1;
	682	end
	683	3'b001://Halfword
	684	begin
	685	case(pcx_packet_d[64+2:64+1])
	686	2'b00:cpx_packet_1[127:0]<={wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48]};
	687	2'b01:cpx_packet_1[127:0]<={wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32]};
	688	2'b10:cpx_packet_1[127:0]<={wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16]};
	689	2'b11:cpx_packet_1[127:0]<={wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0]};
	690	endcase
	691	wb_cycle<=0;
	692	state<=`CPX_READY_1;
	693	end
	694	3'b010://Word
	695	begin
	696	if(pcx_packet_d[64+2]==0)
	697	cpx_packet_1[127:0]<={wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32]};
	698	else
	699	cpx_packet_1[127:0]<={wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0]};
	700	wb_cycle<=0;
	701	state<=`CPX_READY_1;
	702	end
	703	3'b011://Doubleword
	704	begin
	705	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	706	wb_cycle<=0;
	707	state<=`CPX_READY_1;
	708	end
	709	3'b100://Quadword
	710	begin
	711	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	712	wb_cycle<=0;
	713	state<=`CPX_READY_1; // 16 byte access to PROM should just duplicate the data
	714	end
	715	3'b111://Cacheline
	716	begin
	717	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	718	wb_cycle<=0;
	719	state<=`CPX_READY_1; // 16 byte access to PROM should just duplicate the data
	720	end
	721	default:
	722	begin
	723	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	724	wb_cycle<=0;
	725	state<=`PCX_UNKNOWN;
	726	end
	727	endcase
	728	end
	729	5'b00001://Store
	730	begin
	731	cpx_packet_1[143:140]<=4'b0100; // Type
	732	cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/BIS/,2'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	733	// if((pcx_packet_d[110:109]==2'b01) && (pcx_packet_d[64+5:64]==0) && !inval_vect0[3] && !inval_vect1[3]) // Block init store
	734	// state<=`PCX_BIS;
	735	// else
	736	// begin
	737	wb_cycle<=0;
	738	state<=`CPX_READY_1;
	739	// end
	740	end
	741	5'b00010://CAS
	742	begin
	743	cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
	744	cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
	745	cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	746	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	747	state<=`PCX_REQ_STEP2;
	748	end
	749	5'b00100://STRLOAD
	750	begin
	751	cpx_packet_1[143:140]<=4'b0010; // Type
	752	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	753	state<=`PCX_REQ_STEP2;
	754	end
	755	5'b00101://STRSTORE
	756	begin
	757	cpx_packet_1[143:140]<=4'b0110; // Type
	758	cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	759	wb_cycle<=0;
	760	state<=`CPX_READY_1;
	761	end
	762	5'b00110://SWAP/LDSTUB
	763	begin
	764	cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
	765	cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
	766	cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	767	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	768	state<=`PCX_REQ_STEP2;
	769	end
	770	5'b10000://IFILL
	771	begin
	772	cpx_packet_1[143:140]<=4'b0001; // Type
	773	cpx_packet_2[143:140]<=4'b0001; // Type
	774	if(pcx_req_d[4]) // I/O access
	775	begin
	776	if(pcx_packet_d[64+2]==0)
	777	cpx_packet_1[127:0]<={wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32]};
	778	else
	779	cpx_packet_1[127:0]<={wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0]};
	780	state<=`CPX_READY_1;
	781	wb_cycle<=0;
	782	end
	783	else
	784	begin
	785	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	786	state<=`PCX_REQ_STEP2;
	787	end
	788	end
	789	default:
	790	begin
	791	wb_cycle<=0;
	792	state<=`PCX_UNKNOWN;
	793	end
	794	endcase
	795	end
	796	end
	797	`PCX_REQ_STEP2: // IFill, Load/strload, CAS, SWAP, LDSTUB - alwas load
	798	begin
	799	wb_strobe<=1'b1;
	800	if(pcx_packet_d[122:118]==5'b10000)
	801	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b01000};
	802	else
	803	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b1000};
	804	wb_sel<=8'b11111111; // It is always full width for subsequent IFill and load accesses
	805	state<=`PCX_REQ_STEP2_1;
	806	end
	807	`PCX_REQ_STEP2_1:
	808	if(wb_ack==1)
	809	begin
	810	wb_strobe<=0;
	811	wb_sel<=8'b0;
	812	wb_addr<=64'b0;
	813	wb_data_o<=64'b0;
	814	wb_we<=0;
	815	cpx_packet_1[63:0]<=wb_data_i;
	816	if((pcx_packet_d[122:118]!=5'b00000) && (pcx_packet_d[122:118]!=5'b00100))
	817	if(pcx_packet_d[122:118]!=5'b00010) // IFill, SWAP
	818	state<=`PCX_REQ_STEP3;
	819	else
	820	state<=`PCX_REQ_CAS_COMPARE; // CAS
	821	else
	822	begin
	823	wb_cycle<=0;
	824	state<=`CPX_READY_1;
	825	end
	826	end
	827	`PCX_REQ_CAS_COMPARE:
	828	begin
	829	cpx_two_packet<=1;
	830	if(pcx_packet_d[106:104]==3'b010) // 32-bit
	831	case(pcx_packet_d[64+3:64+2])
	832	2'b00:state<=cpx_packet_1[127:96]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	833	2'b01:state<=cpx_packet_1[95:64]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	834	2'b10:state<=cpx_packet_1[63:32]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	835	2'b11:state<=cpx_packet_1[31:0]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	836	endcase
	837	else
	838	if(pcx_packet_d[64+3]==0)
	839	state<=cpx_packet_1[127:64]==pcx_packet_d[63:0] ? `PCX_REQ_STEP3:`CPX_READY_1;
	840	else
	841	state<=cpx_packet_1[63:0]==pcx_packet_d[63:0] ? `PCX_REQ_STEP3:`CPX_READY_1;
	842	end
	843	`PCX_REQ_STEP3: // 256-bit IFILL; CAS, SWAP and LDSTUB store
	844	begin
	845	if(pcx_packet_d[122:118]==5'b10000)
	846	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b10000};
	847	else
	848	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3],3'b000}; // CAS or SWAP save
	849	cpx_two_packet<=1;
	850	if(pcx_packet_d[122:118]==5'b10000)
	851	wb_we<=0;
	852	else
	853	wb_we<=1;
	854	wb_strobe<=1'b1;
	855	if(pcx_packet_d[122:118]==5'b00010) // CAS
	856	if(pcx_packet_d[106:104]==3'b010)
	857	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	858	else
	859	wb_sel<=8'b11111111; //CASX
	860	else
	861	if(pcx_packet_d[122:118]==5'b00110) //SWAP or LDSTUB
	862	if(pcx_packet_d[106:104]==3'b000) //LDSTUB
	863	case(pcx_packet_d[64+2:64])
	864	3'b000:wb_sel<=8'b10000000;
	865	3'b001:wb_sel<=8'b01000000;
	866	3'b010:wb_sel<=8'b00100000;
	867	3'b011:wb_sel<=8'b00010000;
	868	3'b100:wb_sel<=8'b00001000;
	869	3'b101:wb_sel<=8'b00000100;
	870	3'b110:wb_sel<=8'b00000010;
	871	3'b111:wb_sel<=8'b00000001;
	872	endcase
	873	else
	874	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111; ///SWAP is always 32-bit
	875	else
	876	wb_sel<=8'b11111111; // It is always full width for subsequent IFill accesses
	877	if(pcx_packet_d[122:118]==5'b00110) //SWAP or LDSTUB
	878	wb_data_o<={pcx_packet_d[63:32],pcx_packet_d[63:32]};
	879	// wb_data_o<=pcx_packet_d[63:0];
	880	else
	881	wb_data_o<=pcx_packet_2nd[63:0]; // CAS store second packet data
	882	// if(pcx_packet_d[106:104]==3'b010)
	883	// wb_data_o<={pcx_packet_2nd[63:32],pcx_packet_2nd[63:32]}; // CAS store second packet data
	884	// else
	885	// wb_data_o<=pcx_packet_2nd[63:0];
	886	state<=`PCX_REQ_STEP3_1;
	887	end
	888	`PCX_REQ_STEP3_1:
	889	if(wb_ack==1)
	890	begin
	891	wb_strobe<=0;
	892	wb_sel<=8'b0;
	893	wb_addr<=64'b0;
	894	wb_we<=0;
	895	wb_data_o<=64'b0;
	896	if(pcx_packet_d[122:118]==5'b10000) // IFill
	897	begin
	898	cpx_packet_2[127:64]<=wb_data_i;
	899	state<=`PCX_REQ_STEP4;
	900	end
	901	else
	902	begin
	903	wb_cycle<=0;
	904	state<=`CPX_READY_1;
	905	end
	906	end
	907	`PCX_REQ_STEP4: // 256-bit IFILL only
	908	begin
	909	wb_strobe<=1'b1;
	910	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b11000};
	911	wb_sel<=8'b11111111; // It is always full width for subsequent accesses
	912	state<=`PCX_REQ_STEP4_1;
	913	end
	914	`PCX_REQ_STEP4_1:
	915	if(wb_ack==1)
	916	begin
	917	wb_cycle<=0;
	918	wb_strobe<=0;
	919	wb_sel<=8'b0;
	920	wb_addr<=64'b0;
	921	wb_we<=0;
	922	cpx_packet_2[63:0]<=wb_data_i;
	923	state<=`CPX_READY_1;
	924	end
	925	`PCX_BIS: // Block init store
	926	begin
	927	wb_strobe<=1'b1;
	928	wb_we<=1;
	929	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+6],6'b001000};
	930	wb_sel<=8'b11111111;
	931	wb_data_o<=64'b0;
	932	state<=`PCX_BIS_1;
	933	end
	934	`PCX_BIS_1:
	935	if(wb_ack)
	936	begin
	937	wb_strobe<=0;
	938	if(wb_addr[39:0]<(pcx_packet_d[64+39:64]+8*7))
	939	state<=`PCX_BIS_2;
	940	else
	941	begin
	942	wb_cycle<=0;
	943	wb_sel<=0;
	944	wb_we<=0;
	945	wb_addr<=64'b0;
	946	state<=`CPX_READY_1;
	947	end
	948	end
	949	`PCX_BIS_2:
	950	begin
	951	wb_strobe<=1'b1;
	952	wb_addr[5:0]<=wb_addr[5:0]+8;
	953	state<=`PCX_BIS_1;
	954	end
	955	`PCX_FP_1:
	956	begin
	957	fp_pcx<=pcx_packet_d;
	958	fp_req<=1;
	959	state<=`PCX_FP_2;
	960	if(`DEBUGGING)
	961	begin
	962	wb_addr<=pcx_packet_d[103:64];
	963	wb_data_o<=pcx_packet_d[63:0];
	964	wb_sel<=8'h22;
	965	end
	966	end
	967	`PCX_FP_2:
	968	begin
	969	fp_pcx<=pcx_packet_2nd;
	970	state<=`FP_WAIT;
	971	if(`DEBUGGING)
	972	begin
	973	wb_addr<=pcx_packet_2nd[103:64];
	974	wb_data_o<=pcx_packet_d[63:0];
	975	wb_sel<=8'h23;
	976	end
	977	end
	978	`FP_WAIT:
	979	begin
	980	fp_pcx<=124'b0;
	981	fp_req<=0;
	982	if(fp_rdy)
	983	state<=`CPX_FP;
	984	if(`DEBUGGING)
	985	wb_sel<=8'h24;
	986	end
	987	`CPX_FP:
	988	if(fp_cpx[144]) // Packet valid
	989	begin
	990	cpx_packet_1<=fp_cpx;
	991	state<=`CPX_READY_1;
	992	if(`DEBUGGING)
	993	begin
	994	wb_addr<=fp_cpx[63:0];
	995	wb_data_o<=fp_cpx[127:64];
	996	end
	997	end
	998	else
	999	if(!fp_rdy)
	1000	state<=`FP_WAIT; // Else wait for another one if it is not here still
	1001	`CPX_SEND_ETH_IRQ:
	1002	begin
	1003	cpx_packet_1<=145'h1_7_000_000000000000001D_000000000000_001D;
	1004	eth_int_sent<=0;
	1005	state<=`CPX_READY_1;
	1006	end
	1007	`CPX_INT_VEC_DIS:
	1008	begin
	1009	//if(pcx_packet_d[12:10]==3'b000) // Send interrupt only if it is for this core
	1010	cpx_two_packet<=1;
	1011	cpu2<=pcx_packet_d[10];
	1012	cpx_packet_1[144:140]<=5'b10100;
	1013	cpx_packet_1[139:137]<=0;
	1014	cpx_packet_1[136]<=1;
	1015	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	1016	cpx_packet_1[133:130]<=0;
	1017	cpx_packet_1[129]<=pcx_atom_d;
	1018	cpx_packet_1[128]<=0;
	1019	cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],112'b0};
	1020	cpx_packet_2<={9'h170,54'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
	1021	state<=`CPX_READY_1;
	1022	end
	1023	`CPX_READY_1:
	1024	begin
	1025	if(!cpu)
	1026	begin
	1027	cpx_ready<=1;
	1028	cpx_packet<=cpx_packet_1;
	1029	if(othercpuhit[0])
	1030	begin
	1031	cpx1_ready<=1;
	1032	cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b001,pcx_packet_d[64+11:64+6],inval_vect0};
	1033	end
	1034	end
	1035	else
	1036	begin
	1037	cpx1_ready<=1;
	1038	cpx1_packet<=cpx_packet_1;
	1039	if(othercpuhit[0])
	1040	begin
	1041	cpx_ready<=1;
	1042	cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b000,pcx_packet_d[64+11:64+6],inval_vect0};
	1043	end
	1044	end
	1045	cnt<=cnt+1;
	1046	if(`DEBUGGING)
	1047	if(multi_hit \|\| multi_hit1)
	1048	wb_sel<=8'h11;
	1049	state<=`CPX_READY_2;
	1050	end
	1051	`CPX_READY_2:
	1052	begin
	1053	if(cpx_two_packet && !cpu2)
	1054	begin
	1055	cpx_ready<=1;
	1056	cpx_packet<=cpx_packet_2;
	1057	end
	1058	else
	1059	if(cpu2 && othercpuhit[1])
	1060	begin
	1061	cpx_ready<=1;
	1062	cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b000,pcx_packet_d[64+11:64+6],inval_vect1};
	1063	end
	1064	else
	1065	begin
	1066	cpx_ready<=0;
	1067	cpx_packet<=145'b0;
	1068	end
	1069	if(cpx_two_packet && cpu2)
	1070	begin
	1071	cpx1_ready<=1;
	1072	cpx1_packet<=cpx_packet_2;
	1073	end
	1074	else
	1075	if(!cpu2 && othercpuhit[1])
	1076	begin
	1077	cpx1_ready<=1;
	1078	cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b001,pcx_packet_d[64+11:64+6],inval_vect1};
	1079	end
	1080	else
	1081	begin
	1082	cpx1_ready<=0;
	1083	cpx1_packet<=145'b0;
	1084	end
	1085	state<=`PCX_IDLE;
	1086	end
	1087	`PCX_UNKNOWN:
	1088	begin
	1089	wb_sel<=8'b10100101; // Illegal eye-catching value for debugging
	1090	state<=`PCX_IDLE;
	1091	end
	1092	endcase
	1093
	1094	l1dir l1dir_inst(
	1095	.clk(clk),
	1096	.reset(!rstn),
	1097
	1098	.cpu(cpu), // Issuing CPU number
	1099	.strobe(state==`GOT_PCX_REQ),
	1100	.way(pcx_packet[108:107]), // Way to allocate for allocating loads
	1101	.address(pcx_packet[64+39:64]),
	1102	.load(pcx_packet[122:118]==5'b00000),
	1103	.ifill(pcx_packet[122:118]==5'b10000),
	1104	.store(pcx_packet[122:118]==5'b00001),
	1105	.cas(pcx_packet[122:118]==5'b00010),
	1106	.swap(pcx_packet[122:118]==5'b00110),
	1107	.strload(pcx_packet[122:118]==5'b00100),
	1108	.strstore(pcx_packet[122:118]==5'b00101),
	1109	.cacheable((!pcx_packet[117]) && (!pcx_req_d[4])),
	1110	.prefetch(pcx_packet[110]),
	1111	.invalidate(pcx_packet[111]),
	1112	.blockstore(pcx_packet[109] \| pcx_packet[110]),
	1113
	1114	.inval_vect0(inval_vect0), // Invalidation vector
	1115	.inval_vect1(inval_vect1),
	1116	.othercachehit(othercachehit), // Other cache hit in the same CPU, wayval0/wayval1
	1117	.othercpuhit(othercpuhit), // Any cache hit in the other CPU, wayval0/wayval1
	1118	.wayval0(wayval0), // Way valid
	1119	.wayval1(wayval1), // Second way valid for ifill
	1120	.ready(ready) // Directory init done
	1121	);
	1122
	1123	endmodule

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