| 1 | //***************************************************************************** |
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| 2 | // DISCLAIMER OF LIABILITY |
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| 3 | // |
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| 4 | // This file contains proprietary and confidential information of |
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| 5 | // Xilinx, Inc. ("Xilinx"), that is distributed under a license |
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| 6 | // from Xilinx, and may be used, copied and/or disclosed only |
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| 8 | // |
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| 9 | // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION |
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| 10 | // ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER |
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| 11 | // EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT |
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| 13 | // MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx |
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| 19 | // results of the use, of the Materials in terms of correctness, |
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| 20 | // accuracy, reliability or otherwise. |
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| 21 | // |
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| 22 | // Xilinx products are not designed or intended to be fail-safe, |
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| 23 | // or for use in any application requiring fail-safe performance, |
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| 31 | // subject only to applicable laws and regulations governing |
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| 32 | // limitations on product liability. |
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| 33 | // |
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| 34 | // Copyright 2007, 2008 Xilinx, Inc. |
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| 35 | // All rights reserved. |
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| 36 | // |
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| 37 | // This disclaimer and copyright notice must be retained as part |
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| 38 | // of this file at all times. |
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| 39 | //***************************************************************************** |
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| 40 | // ____ ____ |
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| 41 | // / /\/ / |
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| 42 | // /___/ \ / Vendor : Xilinx |
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| 43 | // \ \ \/ Version : 3.6 |
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| 44 | // \ \ Application : MIG |
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| 45 | // / / Filename : sim_tb_top.v |
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| 46 | // /___/ /\ Date Last Modified : $Date: 2010/06/29 12:03:42 $ |
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| 47 | // \ \ / \ Date Created : Mon May 14 2007 |
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| 48 | // \___\/\___\ |
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| 49 | // |
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| 50 | // Device : Virtex-5 |
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| 51 | // Design Name : DDR2 |
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| 52 | // Purpose : This is the simulation testbench which is used to verify the |
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| 53 | // design. The basic clocks and resets to the interface are |
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| 54 | // generated here. This also connects the memory interface to the |
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| 55 | // memory model. |
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| 56 | // Reference: |
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| 57 | // Revision History: |
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| 58 | //***************************************************************************** |
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| 59 | |
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| 60 | `timescale 1ns / 1ps |
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| 61 | |
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| 62 | module sim_tb_top; |
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| 63 | |
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| 64 | // memory controller parameters |
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| 65 | parameter BANK_WIDTH = 2; // # of memory bank addr bits |
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| 66 | parameter CKE_WIDTH = 1; // # of memory clock enable outputs |
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| 67 | parameter CLK_WIDTH = 2; // # of clock outputs |
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| 68 | parameter CLK_TYPE = "SINGLE_ENDED"; // # of clock type |
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| 69 | parameter COL_WIDTH = 10; // # of memory column bits |
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| 70 | parameter CS_NUM = 1; // # of separate memory chip selects |
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| 71 | parameter CS_WIDTH = 1; // # of total memory chip selects |
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| 72 | parameter CS_BITS = 0; // set to log2(CS_NUM) (rounded up) |
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| 73 | parameter DM_WIDTH = 8; // # of data mask bits |
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| 74 | parameter DQ_WIDTH = 64; // # of data width |
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| 75 | parameter DQ_PER_DQS = 8; // # of DQ data bits per strobe |
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| 76 | parameter DQS_WIDTH = 8; // # of DQS strobes |
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| 77 | parameter DQ_BITS = 6; // set to log2(DQS_WIDTH*DQ_PER_DQS) |
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| 78 | parameter DQS_BITS = 3; // set to log2(DQS_WIDTH) |
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| 79 | parameter HIGH_PERFORMANCE_MODE = "TRUE"; // Sets the performance mode for IODELAY elements |
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| 80 | parameter ODT_WIDTH = 1; // # of memory on-die term enables |
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| 81 | parameter ROW_WIDTH = 13; // # of memory row & # of addr bits |
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| 82 | parameter APPDATA_WIDTH = 128; // # of usr read/write data bus bits |
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| 83 | parameter ADDITIVE_LAT = 0; // additive write latency |
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| 84 | parameter BURST_LEN = 4; // burst length (in double words) |
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| 85 | parameter BURST_TYPE = 0; // burst type (=0 seq; =1 interlved) |
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| 86 | parameter CAS_LAT = 3; // CAS latency |
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| 87 | parameter ECC_ENABLE = 0; // enable ECC (=1 enable) |
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| 88 | parameter MULTI_BANK_EN = 1; // enable bank management |
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| 89 | parameter TWO_T_TIME_EN = 1; // 2t timing for unbuffered dimms |
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| 90 | parameter ODT_TYPE = 1; // ODT (=0(none),=1(75),=2(150),=3(50)) |
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| 91 | parameter REDUCE_DRV = 0; // reduced strength mem I/O (=1 yes) |
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| 92 | parameter REG_ENABLE = 0; // registered addr/ctrl (=1 yes) |
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| 93 | parameter TREFI_NS = 7800; // auto refresh interval (ns) |
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| 94 | parameter TRAS = 40000; // active->precharge delay |
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| 95 | parameter TRCD = 15000; // active->read/write delay |
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| 96 | parameter TRFC = 105000; // ref->ref, ref->active delay |
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| 97 | parameter TRP = 15000; // precharge->command delay |
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| 98 | parameter TRTP = 7500; // read->precharge delay |
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| 99 | parameter TWR = 15000; // used to determine wr->prech |
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| 100 | parameter TWTR = 7500; // write->read delay |
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| 101 | parameter SIM_ONLY = 1; // = 0 to allow power up delay |
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| 102 | parameter DEBUG_EN = 0; // Enable debug signals/controls |
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| 103 | parameter RST_ACT_LOW = 1; // =1 for active low reset, =0 for active high |
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| 104 | parameter DLL_FREQ_MODE = "HIGH"; // DCM Frequency range |
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| 105 | parameter CLK_PERIOD = 5000; // Core/Mem clk period (in ps) |
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| 106 | |
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| 107 | localparam DEVICE_WIDTH = 16; // Memory device data width |
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| 108 | localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0; |
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| 109 | localparam real TCYC_200 = 5.0; |
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| 110 | localparam real TPROP_DQS = 0.01; // Delay for DQS signal during Write Operation |
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| 111 | localparam real TPROP_DQS_RD = 0.01; // Delay for DQS signal during Read Operation |
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| 112 | localparam real TPROP_PCB_CTRL = 0.01; // Delay for Address and Ctrl signals |
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| 113 | localparam real TPROP_PCB_DATA = 0.01; // Delay for data signal during Write operation |
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| 114 | localparam real TPROP_PCB_DATA_RD = 0.01; // Delay for data signal during Read operation |
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| 115 | |
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| 116 | |
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| 117 | reg sys_clk; |
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| 118 | wire sys_clk_n; |
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| 119 | wire sys_clk_p; |
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| 120 | reg sys_clk200; |
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| 121 | wire clk200_n; |
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| 122 | wire clk200_p; |
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| 123 | reg sys_rst_n; |
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| 124 | wire sys_rst_out; |
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| 125 | |
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| 126 | |
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| 127 | wire [DQ_WIDTH-1:0] ddr2_dq_sdram; |
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| 128 | wire [DQS_WIDTH-1:0] ddr2_dqs_sdram; |
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| 129 | wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; |
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| 130 | wire [DM_WIDTH-1:0] ddr2_dm_sdram; |
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| 131 | reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp; |
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| 132 | reg [CLK_WIDTH-1:0] ddr2_clk_sdram; |
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| 133 | reg [CLK_WIDTH-1:0] ddr2_clk_n_sdram; |
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| 134 | reg [ROW_WIDTH-1:0] ddr2_address_sdram; |
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| 135 | reg [BANK_WIDTH-1:0] ddr2_ba_sdram; |
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| 136 | reg ddr2_ras_n_sdram; |
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| 137 | reg ddr2_cas_n_sdram; |
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| 138 | reg ddr2_we_n_sdram; |
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| 139 | reg [CS_WIDTH-1:0] ddr2_cs_n_sdram; |
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| 140 | reg [CKE_WIDTH-1:0] ddr2_cke_sdram; |
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| 141 | reg [ODT_WIDTH-1:0] ddr2_odt_sdram; |
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| 142 | |
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| 143 | |
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| 144 | wire [DQ_WIDTH-1:0] ddr2_dq_fpga; |
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| 145 | wire [DQS_WIDTH-1:0] ddr2_dqs_fpga; |
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| 146 | wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga; |
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| 147 | wire [DM_WIDTH-1:0] ddr2_dm_fpga; |
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| 148 | wire [CLK_WIDTH-1:0] ddr2_clk_fpga; |
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| 149 | wire [CLK_WIDTH-1:0] ddr2_clk_n_fpga; |
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| 150 | wire [ROW_WIDTH-1:0] ddr2_address_fpga; |
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| 151 | wire [BANK_WIDTH-1:0] ddr2_ba_fpga; |
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| 152 | wire ddr2_ras_n_fpga; |
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| 153 | wire ddr2_cas_n_fpga; |
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| 154 | wire ddr2_we_n_fpga; |
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| 155 | wire [CS_WIDTH-1:0] ddr2_cs_n_fpga; |
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| 156 | wire [CKE_WIDTH-1:0] ddr2_cke_fpga; |
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| 157 | wire [ODT_WIDTH-1:0] ddr2_odt_fpga; |
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| 158 | |
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| 159 | wire error; |
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| 160 | wire phy_init_done; |
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| 161 | |
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| 162 | |
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| 163 | // Only RDIMM memory parts support the reset signal, |
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| 164 | // hence the ddr2_reset_n signal can be ignored for other memory parts |
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| 165 | wire ddr2_reset_n; |
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| 166 | reg [ROW_WIDTH-1:0] ddr2_address_reg; |
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| 167 | reg [BANK_WIDTH-1:0] ddr2_ba_reg; |
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| 168 | reg [CKE_WIDTH-1:0] ddr2_cke_reg; |
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| 169 | reg ddr2_ras_n_reg; |
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| 170 | reg ddr2_cas_n_reg; |
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| 171 | reg ddr2_we_n_reg; |
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| 172 | reg [CS_WIDTH-1:0] ddr2_cs_n_reg; |
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| 173 | reg [ODT_WIDTH-1:0] ddr2_odt_reg; |
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| 174 | |
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| 175 | //*************************************************************************** |
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| 176 | // Clock generation and reset |
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| 177 | //*************************************************************************** |
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| 178 | |
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| 179 | initial |
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| 180 | sys_clk = 1'b0; |
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| 181 | always |
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| 182 | sys_clk = #(CLK_PERIOD_NS/2) ~sys_clk; |
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| 183 | |
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| 184 | assign sys_clk_p = sys_clk; |
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| 185 | assign sys_clk_n = ~sys_clk; |
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| 186 | |
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| 187 | initial |
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| 188 | sys_clk200 = 1'b0; |
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| 189 | always |
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| 190 | sys_clk200 = #(TCYC_200/2) ~sys_clk200; |
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| 191 | |
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| 192 | assign clk200_p = sys_clk200; |
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| 193 | assign clk200_n = ~sys_clk200; |
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| 194 | |
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| 195 | initial begin |
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| 196 | sys_rst_n = 1'b0; |
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| 197 | #200; |
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| 198 | sys_rst_n = 1'b1; |
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| 199 | end |
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| 200 | assign sys_rst_out = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n; |
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| 201 | |
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| 202 | |
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| 203 | |
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| 204 | |
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| 205 | // ============================================================================= |
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| 206 | // BOARD Parameters |
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| 207 | // ============================================================================= |
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| 208 | // These parameter values can be changed to model varying board delays |
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| 209 | // between the Virtex-5 device and the memory model |
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| 210 | |
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| 211 | |
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| 212 | always @( * ) begin |
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| 213 | ddr2_clk_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_fpga; |
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| 214 | ddr2_clk_n_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_n_fpga; |
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| 215 | ddr2_address_sdram <= #(TPROP_PCB_CTRL) ddr2_address_fpga; |
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| 216 | ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga; |
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| 217 | ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga; |
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| 218 | ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga; |
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| 219 | ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga; |
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| 220 | ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga; |
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| 221 | ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga; |
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| 222 | ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga; |
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| 223 | ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation |
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| 224 | end |
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| 225 | |
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| 226 | assign ddr2_dm_sdram = ddr2_dm_sdram_tmp; |
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| 227 | |
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| 228 | |
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| 229 | // Controlling the bi-directional BUS |
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| 230 | genvar dqwd; |
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| 231 | generate |
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| 232 | for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay |
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| 233 | WireDelay # |
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| 234 | ( |
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| 235 | .Delay_g (TPROP_PCB_DATA), |
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| 236 | .Delay_rd (TPROP_PCB_DATA_RD) |
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| 237 | ) |
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| 238 | u_delay_dq |
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| 239 | ( |
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| 240 | .A (ddr2_dq_fpga[dqwd]), |
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| 241 | .B (ddr2_dq_sdram[dqwd]), |
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| 242 | .reset (sys_rst_n) |
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| 243 | ); |
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| 244 | end |
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| 245 | endgenerate |
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| 246 | |
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| 247 | genvar dqswd; |
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| 248 | generate |
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| 249 | for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay |
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| 250 | WireDelay # |
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| 251 | ( |
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| 252 | .Delay_g (TPROP_DQS), |
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| 253 | .Delay_rd (TPROP_DQS_RD) |
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| 254 | ) |
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| 255 | u_delay_dqs |
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| 256 | ( |
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| 257 | .A (ddr2_dqs_fpga[dqswd]), |
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| 258 | .B (ddr2_dqs_sdram[dqswd]), |
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| 259 | .reset (sys_rst_n) |
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| 260 | ); |
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| 261 | |
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| 262 | WireDelay # |
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| 263 | ( |
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| 264 | .Delay_g (TPROP_DQS), |
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| 265 | .Delay_rd (TPROP_DQS_RD) |
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| 266 | ) |
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| 267 | u_delay_dqs_n |
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| 268 | ( |
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| 269 | .A (ddr2_dqs_n_fpga[dqswd]), |
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| 270 | .B (ddr2_dqs_n_sdram[dqswd]), |
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| 271 | .reset (sys_rst_n) |
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| 272 | ); |
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| 273 | end |
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| 274 | endgenerate |
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| 275 | |
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| 276 | |
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| 277 | |
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| 278 | //*************************************************************************** |
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| 279 | // FPGA memory controller |
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| 280 | //*************************************************************************** |
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| 281 | |
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| 282 | dram # |
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| 283 | ( |
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| 284 | .BANK_WIDTH (BANK_WIDTH), |
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| 285 | .CKE_WIDTH (CKE_WIDTH), |
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| 286 | .CLK_WIDTH (CLK_WIDTH), |
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| 287 | .COL_WIDTH (COL_WIDTH), |
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| 288 | .CS_NUM (CS_NUM), |
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| 289 | .CS_WIDTH (CS_WIDTH), |
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| 290 | .CS_BITS (CS_BITS), |
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| 291 | .DM_WIDTH (DM_WIDTH), |
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| 292 | .DQ_WIDTH (DQ_WIDTH), |
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| 293 | .DQ_PER_DQS (DQ_PER_DQS), |
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| 294 | .DQ_BITS (DQ_BITS), |
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| 295 | .DQS_WIDTH (DQS_WIDTH), |
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| 296 | .DQS_BITS (DQS_BITS), |
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| 297 | .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), |
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| 298 | .ODT_WIDTH (ODT_WIDTH), |
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| 299 | .ROW_WIDTH (ROW_WIDTH), |
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| 300 | .APPDATA_WIDTH (APPDATA_WIDTH), |
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| 301 | .ADDITIVE_LAT (ADDITIVE_LAT), |
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| 302 | .BURST_LEN (BURST_LEN), |
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| 303 | .BURST_TYPE (BURST_TYPE), |
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| 304 | .CAS_LAT (CAS_LAT), |
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| 305 | .ECC_ENABLE (ECC_ENABLE), |
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| 306 | .MULTI_BANK_EN (MULTI_BANK_EN), |
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| 307 | .ODT_TYPE (ODT_TYPE), |
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| 308 | .REDUCE_DRV (REDUCE_DRV), |
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| 309 | .REG_ENABLE (REG_ENABLE), |
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| 310 | .TREFI_NS (TREFI_NS), |
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| 311 | .TRAS (TRAS), |
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| 312 | .TRCD (TRCD), |
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| 313 | .TRFC (TRFC), |
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| 314 | .TRP (TRP), |
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| 315 | .TRTP (TRTP), |
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| 316 | .TWR (TWR), |
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| 317 | .TWTR (TWTR), |
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| 318 | .SIM_ONLY (SIM_ONLY), |
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| 319 | .RST_ACT_LOW (RST_ACT_LOW), |
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| 320 | .CLK_TYPE (CLK_TYPE), |
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| 321 | .DLL_FREQ_MODE (DLL_FREQ_MODE), |
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| 322 | .CLK_PERIOD (CLK_PERIOD) |
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| 323 | ) |
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| 324 | u_mem_controller |
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| 325 | ( |
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| 326 | .sys_clk (sys_clk_p), |
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| 327 | .idly_clk_200 (clk200_p), |
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| 328 | .sys_rst_n (sys_rst_out), |
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| 329 | .ddr2_ras_n (ddr2_ras_n_fpga), |
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| 330 | .ddr2_cas_n (ddr2_cas_n_fpga), |
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| 331 | .ddr2_we_n (ddr2_we_n_fpga), |
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| 332 | .ddr2_cs_n (ddr2_cs_n_fpga), |
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| 333 | .ddr2_cke (ddr2_cke_fpga), |
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| 334 | .ddr2_odt (ddr2_odt_fpga), |
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| 335 | .ddr2_dm (ddr2_dm_fpga), |
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| 336 | .ddr2_dq (ddr2_dq_fpga), |
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| 337 | .ddr2_dqs (ddr2_dqs_fpga), |
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| 338 | .ddr2_dqs_n (ddr2_dqs_n_fpga), |
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| 339 | .ddr2_ck (ddr2_clk_fpga), |
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| 340 | .ddr2_ck_n (ddr2_clk_n_fpga), |
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| 341 | .ddr2_ba (ddr2_ba_fpga), |
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| 342 | .ddr2_a (ddr2_address_fpga), |
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| 343 | //.error (error), |
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| 344 | |
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| 345 | |
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| 346 | .phy_init_done (phy_init_done) |
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| 347 | ); |
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| 348 | |
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| 349 | // Extra one clock pipelining for RDIMM address and |
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| 350 | // control signals is implemented here (Implemented external to memory model) |
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| 351 | always @( posedge ddr2_clk_sdram[0] ) begin |
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| 352 | if ( ddr2_reset_n == 1'b0 ) begin |
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| 353 | ddr2_ras_n_reg <= 1'b1; |
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| 354 | ddr2_cas_n_reg <= 1'b1; |
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| 355 | ddr2_we_n_reg <= 1'b1; |
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| 356 | ddr2_cs_n_reg <= {CS_WIDTH{1'b1}}; |
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| 357 | ddr2_odt_reg <= 1'b0; |
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| 358 | end |
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| 359 | else begin |
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| 360 | ddr2_address_reg <= #(CLK_PERIOD_NS/2) ddr2_address_sdram; |
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| 361 | ddr2_ba_reg <= #(CLK_PERIOD_NS/2) ddr2_ba_sdram; |
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| 362 | ddr2_ras_n_reg <= #(CLK_PERIOD_NS/2) ddr2_ras_n_sdram; |
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| 363 | ddr2_cas_n_reg <= #(CLK_PERIOD_NS/2) ddr2_cas_n_sdram; |
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| 364 | ddr2_we_n_reg <= #(CLK_PERIOD_NS/2) ddr2_we_n_sdram; |
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| 365 | ddr2_cs_n_reg <= #(CLK_PERIOD_NS/2) ddr2_cs_n_sdram; |
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| 366 | ddr2_odt_reg <= #(CLK_PERIOD_NS/2) ddr2_odt_sdram; |
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| 367 | end |
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| 368 | end |
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| 369 | |
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| 370 | // to avoid tIS violations on CKE when reset is deasserted |
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| 371 | always @( posedge ddr2_clk_n_sdram[0] ) |
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| 372 | if ( ddr2_reset_n == 1'b0 ) |
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| 373 | ddr2_cke_reg <= 1'b0; |
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| 374 | else |
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| 375 | ddr2_cke_reg <= #(CLK_PERIOD_NS) ddr2_cke_sdram; |
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| 376 | |
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| 377 | //*************************************************************************** |
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| 378 | // Memory model instances |
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| 379 | //*************************************************************************** |
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| 380 | |
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| 381 | genvar i, j; |
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| 382 | generate |
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| 383 | if (DEVICE_WIDTH == 16) begin |
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| 384 | // if memory part is x16 |
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| 385 | if ( REG_ENABLE ) begin |
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| 386 | // if the memory part is Registered DIMM |
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| 387 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 388 | for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen |
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| 389 | ddr2_model u_mem0 |
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| 390 | ( |
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| 391 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 392 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 393 | .cke (ddr2_cke_reg[j]), |
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| 394 | .cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]), |
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| 395 | .ras_n (ddr2_ras_n_reg), |
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| 396 | .cas_n (ddr2_cas_n_reg), |
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| 397 | .we_n (ddr2_we_n_reg), |
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| 398 | .dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), |
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| 399 | .ba (ddr2_ba_reg), |
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| 400 | .addr (ddr2_address_reg), |
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| 401 | .dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]), |
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| 402 | .dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]), |
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| 403 | .dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]), |
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| 404 | .rdqs_n (), |
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| 405 | .odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH]) |
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| 406 | ); |
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| 407 | end |
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| 408 | end |
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| 409 | end |
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| 410 | else begin |
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| 411 | // if the memory part is component or unbuffered DIMM |
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| 412 | if ( DQ_WIDTH%16 ) begin |
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| 413 | // for the memory part x16, if the data width is not multiple |
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| 414 | // of 16, memory models are instantiated for all data with x16 |
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| 415 | // memory model and except for MSB data. For the MSB data |
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| 416 | // of 8 bits, all memory data, strobe and mask data signals are |
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| 417 | // replicated to make it as x16 part. For example if the design |
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| 418 | // is generated for data width of 72, memory model x16 parts |
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| 419 | // instantiated for 4 times with data ranging from 0 to 63. |
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| 420 | // For MSB data ranging from 64 to 71, one x16 memory model |
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| 421 | // by replicating the 8-bit data twice and similarly |
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| 422 | // the case with data mask and strobe. |
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| 423 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 424 | for(i = 0; i < DQ_WIDTH/16 ; i = i+1) begin : gen |
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| 425 | ddr2_model u_mem0 |
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| 426 | ( |
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| 427 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 428 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 429 | .cke (ddr2_cke_sdram[j]), |
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| 430 | .cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
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| 431 | .ras_n (ddr2_ras_n_sdram), |
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| 432 | .cas_n (ddr2_cas_n_sdram), |
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| 433 | .we_n (ddr2_we_n_sdram), |
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| 434 | .dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), |
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| 435 | .ba (ddr2_ba_sdram), |
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| 436 | .addr (ddr2_address_sdram), |
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| 437 | .dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]), |
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| 438 | .dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]), |
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| 439 | .dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]), |
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| 440 | .rdqs_n (), |
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| 441 | .odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
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| 442 | ); |
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| 443 | end |
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| 444 | ddr2_model u_mem1 |
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| 445 | ( |
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| 446 | .ck (ddr2_clk_sdram[CLK_WIDTH-1]), |
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| 447 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH-1]), |
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| 448 | .cke (ddr2_cke_sdram[j]), |
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| 449 | .cs_n (ddr2_cs_n_sdram[CS_WIDTH-1]), |
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| 450 | .ras_n (ddr2_ras_n_sdram), |
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| 451 | .cas_n (ddr2_cas_n_sdram), |
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| 452 | .we_n (ddr2_we_n_sdram), |
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| 453 | .dm_rdqs ({ddr2_dm_sdram[DM_WIDTH - 1], |
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| 454 | ddr2_dm_sdram[DM_WIDTH - 1]}), |
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| 455 | .ba (ddr2_ba_sdram), |
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| 456 | .addr (ddr2_address_sdram), |
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| 457 | .dq ({ddr2_dq_sdram[DQ_WIDTH - 1 : DQ_WIDTH - 8], |
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| 458 | ddr2_dq_sdram[DQ_WIDTH - 1 : DQ_WIDTH - 8]}), |
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| 459 | .dqs ({ddr2_dqs_sdram[DQS_WIDTH - 1], |
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| 460 | ddr2_dqs_sdram[DQS_WIDTH - 1]}), |
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| 461 | .dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH - 1], |
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| 462 | ddr2_dqs_n_sdram[DQS_WIDTH - 1]}), |
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| 463 | .rdqs_n (), |
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| 464 | .odt (ddr2_odt_sdram[ODT_WIDTH-1]) |
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| 465 | ); |
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| 466 | end |
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| 467 | end |
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| 468 | else begin |
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| 469 | // if the data width is multiple of 16 |
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| 470 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 471 | for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen |
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| 472 | ddr2_model u_mem0 |
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| 473 | ( |
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| 474 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 475 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 476 | .cke (ddr2_cke_sdram[j]), |
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| 477 | .cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
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| 478 | .ras_n (ddr2_ras_n_sdram), |
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| 479 | .cas_n (ddr2_cas_n_sdram), |
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| 480 | .we_n (ddr2_we_n_sdram), |
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| 481 | .dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), |
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| 482 | .ba (ddr2_ba_sdram), |
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| 483 | .addr (ddr2_address_sdram), |
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| 484 | .dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]), |
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| 485 | .dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]), |
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| 486 | .dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]), |
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| 487 | .rdqs_n (), |
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| 488 | .odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
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| 489 | ); |
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| 490 | end |
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| 491 | end |
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| 492 | end |
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| 493 | end |
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| 494 | |
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| 495 | end else |
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| 496 | if (DEVICE_WIDTH == 8) begin |
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| 497 | // if the memory part is x8 |
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| 498 | if ( REG_ENABLE ) begin |
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| 499 | // if the memory part is Registered DIMM |
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| 500 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 501 | for(i = 0; i < DQ_WIDTH/DQ_PER_DQS; i = i+1) begin : gen |
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| 502 | ddr2_model u_mem0 |
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| 503 | ( |
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| 504 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 505 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 506 | .cke (ddr2_cke_reg[j]), |
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| 507 | .cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]), |
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| 508 | .ras_n (ddr2_ras_n_reg), |
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| 509 | .cas_n (ddr2_cas_n_reg), |
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| 510 | .we_n (ddr2_we_n_reg), |
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| 511 | .dm_rdqs (ddr2_dm_sdram[i]), |
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| 512 | .ba (ddr2_ba_reg), |
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| 513 | .addr (ddr2_address_reg), |
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| 514 | .dq (ddr2_dq_sdram[(8*(i+1))-1 : i*8]), |
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| 515 | .dqs (ddr2_dqs_sdram[i]), |
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| 516 | .dqs_n (ddr2_dqs_n_sdram[i]), |
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| 517 | .rdqs_n (), |
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| 518 | .odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH]) |
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| 519 | ); |
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| 520 | end |
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| 521 | end |
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| 522 | end |
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| 523 | else begin |
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| 524 | // if the memory part is component or unbuffered DIMM |
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| 525 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 526 | for(i = 0; i < DQS_WIDTH; i = i+1) begin : gen |
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| 527 | ddr2_model u_mem0 |
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| 528 | ( |
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| 529 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 530 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 531 | .cke (ddr2_cke_sdram[j]), |
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| 532 | .cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
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| 533 | .ras_n (ddr2_ras_n_sdram), |
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| 534 | .cas_n (ddr2_cas_n_sdram), |
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| 535 | .we_n (ddr2_we_n_sdram), |
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| 536 | .dm_rdqs (ddr2_dm_sdram[i]), |
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| 537 | .ba (ddr2_ba_sdram), |
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| 538 | .addr (ddr2_address_sdram), |
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| 539 | .dq (ddr2_dq_sdram[(8*(i+1))-1 : i*8]), |
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| 540 | .dqs (ddr2_dqs_sdram[i]), |
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| 541 | .dqs_n (ddr2_dqs_n_sdram[i]), |
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| 542 | .rdqs_n (), |
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| 543 | .odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
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| 544 | ); |
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| 545 | end |
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| 546 | end |
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| 547 | end |
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| 548 | |
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| 549 | end else |
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| 550 | if (DEVICE_WIDTH == 4) begin |
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| 551 | // if the memory part is x4 |
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| 552 | if ( REG_ENABLE ) begin |
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| 553 | // if the memory part is Registered DIMM |
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| 554 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 555 | for(i = 0; i < DQS_WIDTH; i = i+1) begin : gen |
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| 556 | ddr2_model u_mem0 |
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| 557 | ( |
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| 558 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 559 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 560 | .cke (ddr2_cke_reg[j]), |
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| 561 | .cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]), |
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| 562 | .ras_n (ddr2_ras_n_reg), |
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| 563 | .cas_n (ddr2_cas_n_reg), |
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| 564 | .we_n (ddr2_we_n_reg), |
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| 565 | .dm_rdqs (ddr2_dm_sdram[i]), |
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| 566 | .ba (ddr2_ba_reg), |
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| 567 | .addr (ddr2_address_reg), |
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| 568 | .dq (ddr2_dq_sdram[(4*(i+1))-1 : i*4]), |
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| 569 | .dqs (ddr2_dqs_sdram[i]), |
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| 570 | .dqs_n (ddr2_dqs_n_sdram[i]), |
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| 571 | .rdqs_n (), |
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| 572 | .odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH]) |
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| 573 | ); |
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| 574 | end |
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| 575 | end |
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| 576 | end |
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| 577 | else begin |
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| 578 | // if the memory part is component or unbuffered DIMM |
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| 579 | for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs |
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| 580 | for(i = 0; i < DQS_WIDTH; i = i+1) begin : gen |
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| 581 | ddr2_model u_mem0 |
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| 582 | ( |
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| 583 | .ck (ddr2_clk_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 584 | .ck_n (ddr2_clk_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
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| 585 | .cke (ddr2_cke_sdram[j]), |
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| 586 | .cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
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| 587 | .ras_n (ddr2_ras_n_sdram), |
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| 588 | .cas_n (ddr2_cas_n_sdram), |
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| 589 | .we_n (ddr2_we_n_sdram), |
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| 590 | .dm_rdqs (ddr2_dm_sdram[i]), |
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| 591 | .ba (ddr2_ba_sdram), |
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| 592 | .addr (ddr2_address_sdram), |
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| 593 | .dq (ddr2_dq_sdram[(4*(i+1))-1 : i*4]), |
|---|
| 594 | .dqs (ddr2_dqs_sdram[i]), |
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| 595 | .dqs_n (ddr2_dqs_n_sdram[i]), |
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| 596 | .rdqs_n (), |
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| 597 | .odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
|---|
| 598 | ); |
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| 599 | end |
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| 600 | end |
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| 601 | end |
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| 602 | end |
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| 603 | endgenerate |
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| 604 | |
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| 605 | |
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| 606 | endmodule |
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