1 | |
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2 | test.o: file format elf64-sparc |
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3 | |
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4 | |
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5 | Disassembly of section .text: |
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6 | |
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7 | 0000000000000000 <main>: |
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8 | 0: 9d e3 bf 50 save %sp, -176, %sp |
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9 | 4: 01 00 00 00 nop |
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10 | 8: 01 00 00 00 nop |
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11 | c: 01 00 00 00 nop |
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12 | 10: 01 00 00 00 nop |
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13 | 14: 03 00 00 00 sethi %hi(0), %g1 |
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14 | 18: 05 00 01 00 sethi %hi(0x40000), %g2 |
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15 | 1c: 82 10 60 00 mov %g1, %g1 |
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16 | 20: 84 10 a0 c0 or %g2, 0xc0, %g2 |
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17 | 24: 83 28 70 20 sllx %g1, 0x20, %g1 |
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18 | 28: 84 10 80 01 or %g2, %g1, %g2 |
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19 | 2c: 81 c0 80 00 jmp %g2 |
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20 | 30: 01 00 00 00 nop |
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21 | 34: 01 00 00 00 nop |
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22 | 38: 01 00 00 00 nop |
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23 | 3c: 01 00 00 00 nop |
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24 | 40: 01 00 00 00 nop |
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25 | 44: b5 80 20 05 wr %g0, 5, %asr26 |
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26 | 48: a2 10 20 00 clr %l1 |
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27 | 4c: 82 10 20 a9 mov 0xa9, %g1 |
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28 | 50: 83 28 70 20 sllx %g1, 0x20, %g1 |
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29 | 54: e2 70 60 00 stx %l1, [ %g1 ] |
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30 | 58: e2 70 60 40 stx %l1, [ %g1 + 0x40 ] |
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31 | 5c: e2 70 60 80 stx %l1, [ %g1 + 0x80 ] |
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32 | 60: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ] |
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33 | 64: a2 10 20 00 clr %l1 |
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34 | 68: 82 10 20 10 mov 0x10, %g1 |
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35 | 6c: e2 f0 48 40 stxa %l1, [ %g1 ] #ASI_DCACHE_INVALIDATE |
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36 | 70: a2 10 20 03 mov 3, %l1 |
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37 | 74: e2 f0 08 a0 stxa %l1, [ %g0 ] #ASI_LSU_CONTROL_REG |
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38 | 78: a3 48 00 00 rdhpr %hpstate, %l1 |
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39 | 7c: 81 9c 68 20 wrhpr %l1, 0x820, %hpstate |
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40 | 80: 87 80 20 25 wr %g0, 0x25, %asi |
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41 | 84: c0 f0 23 c0 stxa %g0, [ 0x3c0 ] %asi |
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42 | 88: c0 f0 23 c8 stxa %g0, [ 0x3c8 ] %asi |
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43 | 8c: c0 f0 23 d0 stxa %g0, [ 0x3d0 ] %asi |
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44 | 90: c0 f0 23 d8 stxa %g0, [ 0x3d8 ] %asi |
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45 | 94: c0 f0 23 e0 stxa %g0, [ 0x3e0 ] %asi |
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46 | 98: c0 f0 23 e8 stxa %g0, [ 0x3e8 ] %asi |
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47 | 9c: c0 f0 23 f0 stxa %g0, [ 0x3f0 ] %asi |
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48 | a0: c0 f0 23 f8 stxa %g0, [ 0x3f8 ] %asi |
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49 | a4: 8f 90 20 00 wrpr 0, %tl |
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50 | a8: a1 90 20 00 wrpr 0, %gl |
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51 | ac: 8d 80 20 00 wr %g0, 0, %fprs |
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52 | b0: 85 80 20 00 wr %g0, 0, %ccr |
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53 | b4: 87 80 20 00 wr %g0, 0, %asi |
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54 | b8: 84 10 20 00 clr %g2 |
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55 | bc: 89 90 80 00 wrpr %g2, %tick |
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56 | c0: 84 10 20 00 clr %g2 |
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57 | c4: b1 80 80 00 mov %g2, %asr24 |
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58 | c8: 84 10 20 01 mov 1, %g2 |
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59 | cc: 85 28 b0 3f sllx %g2, 0x3f, %g2 |
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60 | d0: af 80 80 00 mov %g2, %asr23 |
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61 | d4: b3 80 80 00 mov %g2, %asr25 |
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62 | d8: bf 98 80 00 wrhpr %g2, %hstick_cmpr |
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63 | dc: 81 80 00 00 mov %g0, %y |
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64 | e0: 91 90 20 0f wrpr 0xf, %pil |
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65 | e4: 93 90 20 00 wrpr 0, %cwp |
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66 | e8: 95 90 20 06 wrpr 6, %cansave |
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67 | ec: 97 90 20 00 wrpr 0, %canrestore |
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68 | f0: 9b 90 20 00 wrpr 0, %otherwin |
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69 | f4: 99 90 20 07 wrpr 7, %cleanwin |
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70 | f8: 9d 90 20 07 wrpr 7, %wstate |
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71 | fc: 82 10 20 18 mov 0x18, %g1 |
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72 | 100: c0 f0 0a 01 stxa %g0, [ %g0 + %g1 ] #ASI_IMMU |
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73 | 104: c0 f0 0b 01 stxa %g0, [ %g0 + %g1 ] #ASI_DMMU |
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74 | 108: a2 10 20 03 mov 3, %l1 |
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75 | 10c: e2 f0 09 60 stxa %l1, [ %g0 ] #ASI_ESTATE_ERROR_EN |
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76 | 110: a2 10 20 03 mov 3, %l1 |
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77 | 114: 82 10 20 aa mov 0xaa, %g1 |
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78 | 118: 83 28 70 20 sllx %g1, 0x20, %g1 |
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79 | 11c: e2 70 60 00 stx %l1, [ %g1 ] |
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80 | 120: e2 70 60 40 stx %l1, [ %g1 + 0x40 ] |
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81 | 124: e2 70 60 80 stx %l1, [ %g1 + 0x80 ] |
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82 | 128: e2 70 60 c0 stx %l1, [ %g1 + 0xc0 ] |
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83 | 12c: a3 46 80 00 rd %asr26, %l1 |
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84 | 130: 03 00 00 07 sethi %hi(0x1c00), %g1 |
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85 | 134: 82 10 63 00 or %g1, 0x300, %g1 ! 1f00 <main+0x1f00> |
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86 | 138: a2 0c 40 01 and %l1, %g1, %l1 |
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87 | 13c: a3 34 70 08 srlx %l1, 8, %l1 |
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88 | 140: 03 00 00 00 sethi %hi(0), %g1 |
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89 | 144: 05 00 01 30 sethi %hi(0x4c000), %g2 |
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90 | 148: 82 10 60 00 mov %g1, %g1 |
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91 | 14c: 84 10 a0 00 mov %g2, %g2 |
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92 | 150: 83 28 70 20 sllx %g1, 0x20, %g1 |
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93 | 154: 84 10 80 01 or %g2, %g1, %g2 |
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94 | 158: a3 2c 70 03 sllx %l1, 3, %l1 |
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95 | 15c: c4 58 80 11 ldx [ %g2 + %l1 ], %g2 |
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96 | 160: 82 10 20 80 mov 0x80, %g1 |
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97 | 164: c4 f0 4b 00 stxa %g2, [ %g1 ] #ASI_DMMU |
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98 | 168: 2f 00 02 00 sethi %hi(0x80000), %l7 |
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99 | 16c: 8b 9d c0 00 wrhpr %l7, %htba |
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100 | 170: 21 00 00 00 sethi %hi(0), %l0 |
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101 | 174: 03 00 01 30 sethi %hi(0x4c000), %g1 |
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102 | 178: a0 14 20 00 mov %l0, %l0 |
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103 | 17c: 82 10 61 40 or %g1, 0x140, %g1 |
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104 | 180: a1 2c 30 20 sllx %l0, 0x20, %l0 |
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105 | 184: 82 10 40 10 or %g1, %l0, %g1 |
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106 | 188: 85 28 b0 07 sllx %g2, 7, %g2 |
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107 | 18c: 82 00 40 02 add %g1, %g2, %g1 |
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108 | 190: e2 58 40 00 ldx [ %g1 ], %l1 |
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109 | 194: e2 f0 06 e0 stxa %l1, [ %g0 ] (55) |
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110 | 198: e2 58 60 08 ldx [ %g1 + 8 ], %l1 |
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111 | 19c: e2 f0 07 e0 stxa %l1, [ %g0 ] (63) |
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112 | 1a0: e2 58 60 10 ldx [ %g1 + 0x10 ], %l1 |
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113 | 1a4: e2 f0 06 a0 stxa %l1, [ %g0 ] (53) |
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114 | 1a8: e2 58 60 20 ldx [ %g1 + 0x20 ], %l1 |
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115 | 1ac: e2 f0 06 c0 stxa %l1, [ %g0 ] (54) |
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116 | 1b0: e2 58 60 18 ldx [ %g1 + 0x18 ], %l1 |
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117 | 1b4: e2 f0 07 a0 stxa %l1, [ %g0 ] (61) |
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118 | 1b8: e2 58 60 28 ldx [ %g1 + 0x28 ], %l1 |
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119 | 1bc: e2 f0 07 c0 stxa %l1, [ %g0 ] (62) |
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120 | 1c0: e2 58 60 40 ldx [ %g1 + 0x40 ], %l1 |
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121 | 1c4: e2 f0 06 60 stxa %l1, [ %g0 ] #ASI_PCACHE_SNOOP_TAG |
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122 | 1c8: e2 58 60 48 ldx [ %g1 + 0x48 ], %l1 |
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123 | 1cc: e2 f0 07 60 stxa %l1, [ %g0 ] #ASI_WCACHE_SNOOP_TAG |
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124 | 1d0: e2 58 60 50 ldx [ %g1 + 0x50 ], %l1 |
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125 | 1d4: e2 f0 06 20 stxa %l1, [ %g0 ] #ASI_PCACHE_DATA |
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126 | 1d8: e2 58 60 60 ldx [ %g1 + 0x60 ], %l1 |
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127 | 1dc: e2 f0 06 40 stxa %l1, [ %g0 ] #ASI_PCACHE_TAG |
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128 | 1e0: e2 58 60 58 ldx [ %g1 + 0x58 ], %l1 |
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129 | 1e4: e2 f0 07 20 stxa %l1, [ %g0 ] #ASI_WCACHE_DATA |
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130 | 1e8: e2 58 60 68 ldx [ %g1 + 0x68 ], %l1 |
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131 | 1ec: e2 f0 07 40 stxa %l1, [ %g0 ] #ASI_WCACHE_TAG |
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132 | 1f0: 94 10 20 80 mov 0x80, %o2 |
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133 | 1f4: c0 f2 8a e0 stxa %g0, [ %o2 ] #ASI_IMMU_DEMAP |
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134 | 1f8: c0 f2 8b e0 stxa %g0, [ %o2 ] #ASI_DMMU_DEMAP |
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135 | 1fc: a2 10 20 08 mov 8, %l1 |
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136 | 200: c0 f4 44 20 stxa %g0, [ %l1 ] #ASI_MMU |
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137 | 204: a2 10 20 10 mov 0x10, %l1 |
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138 | 208: c0 f4 44 20 stxa %g0, [ %l1 ] #ASI_MMU |
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139 | 20c: a2 10 20 0f mov 0xf, %l1 |
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140 | 210: e2 f0 08 a0 stxa %l1, [ %g0 ] #ASI_LSU_CONTROL_REG |
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141 | 214: 03 00 00 00 sethi %hi(0), %g1 |
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142 | 218: 05 00 05 10 sethi %hi(0x144000), %g2 |
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143 | 21c: 82 10 60 00 mov %g1, %g1 |
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144 | 220: 84 10 a0 00 mov %g2, %g2 |
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145 | 224: 83 28 70 20 sllx %g1, 0x20, %g1 |
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146 | 228: 84 10 80 01 or %g2, %g1, %g2 |
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147 | 22c: 87 48 00 00 rdhpr %hpstate, %g3 |
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148 | 230: 8f 90 20 01 wrpr 1, %tl |
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149 | 234: 88 10 20 00 clr %g4 |
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150 | 238: 83 99 00 00 wrhpr %g4, %htstate |
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151 | 23c: 8f 90 20 00 wrpr 0, %tl |
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152 | 240: 90 10 20 00 clr %o0 |
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153 | 244: 81 c0 80 00 jmp %g2 |
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154 | 248: 81 98 28 00 wrhpr 0x800, %hpstate |
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155 | 24c: 01 00 00 00 nop |
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156 | 250: 01 00 00 00 nop |
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157 | 254: 82 10 20 0f mov 0xf, %g1 ! f <main+0xf> |
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158 | 258: c2 f0 08 a0 stxa %g1, [ %g0 ] #ASI_LSU_CONTROL_REG |
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159 | 25c: c0 f0 08 60 stxa %g0, [ %g0 ] #ASI_DCACHE_UTAG |
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160 | 260: 83 48 00 00 rdhpr %hpstate, %g1 |
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161 | 264: 01 00 00 00 nop |
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162 | 268: 01 00 00 00 nop |
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163 | 26c: 01 00 00 00 nop |
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164 | 270: 01 00 00 00 nop |
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165 | 274: 82 10 20 00 clr %g1 ! 0 <main> |
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166 | 278: 83 38 60 00 sra %g1, 0, %g1 |
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167 | 27c: b0 10 00 01 mov %g1, %i0 |
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168 | 280: 81 cf e0 08 rett %i7 + 8 |
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169 | 284: 01 00 00 00 nop |
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