source: XOpenSparcT1/trunk/sw/uart.h @ 32

Revision 32, 5.5 KB checked in by pntsvt00, 14 years ago (diff)

aggiunti file per programma uart e linker script

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1#ifndef _UART_H_
2#define _UART_H_
3void uart_init(char);
4void uart_putc(char, char);
5void uart_puts(char, char*);
6void uart_putc_noblock(char, char);
7char uart_getc(char);
8int uart_check_for_char(char);
9void uart_rxint_enable(char);
10void uart_rxint_disable(char);
11void uart_txint_enable(char);
12void uart_txint_disable(char);
13char uart_get_iir(char);
14char uart_get_lsr(char);
15char uart_get_msr(char);
16
17#define DEFAULT_UART 0 /* Default UART to use */
18
19
20#define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
21#define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
22#define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
23#define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
24#define UART_IER        1       /* Out: Interrupt Enable Register */
25#define UART_IIR        2       /* In:  Interrupt ID Register */
26#define UART_FCR        2       /* Out: FIFO Control Register */
27#define UART_EFR        2       /* I/O: Extended Features Register */
28/* (DLAB=1, 16C660 only) */
29#define UART_LCR        3       /* Out: Line Control Register */
30#define UART_MCR        4       /* Out: Modem Control Register */
31#define UART_LSR        5       /* In:  Line Status Register */
32#define UART_MSR        6       /* In:  Modem Status Register */
33#define UART_SCR        7       /* I/O: Scratch Register */
34
35/*
36 * These are the definitions for the FIFO Control Register
37 * (16650 only)
38 */
39#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
40#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
41#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
42#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
43#define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
44#define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
45#define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
46#define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
47#define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
48/* 16650 redefinitions */
49#define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
50#define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
51#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
52#define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
53#define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
54#define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
55#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
56#define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
57
58/*
59 * These are the definitions for the Line Control Register
60 *
61 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
62 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
63 */
64#define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
65#define UART_LCR_SBC    0x40    /* Set break control */
66#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
67#define UART_LCR_EPAR   0x10    /* Even parity select */
68#define UART_LCR_PARITY 0x08    /* Parity Enable */
69#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
70#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
71#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
72#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
73#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
74
75/*
76 * These are the definitions for the Line Status Register
77 */
78#define UART_LSR_TEMT   0x40    /* Transmitter empty */
79#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
80#define UART_LSR_BI     0x10    /* Break interrupt indicator */
81#define UART_LSR_FE     0x08    /* Frame error indicator */
82#define UART_LSR_PE     0x04    /* Parity error indicator */
83#define UART_LSR_OE     0x02    /* Overrun error indicator */
84#define UART_LSR_DR     0x01    /* Receiver data ready */
85
86/*
87 * These are the definitions for the Interrupt Identification Register
88 */
89#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
90#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
91
92#define UART_IIR_MSI    0x00    /* Modem status interrupt */
93#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
94#define UART_IIR_TOI    0x0c    /* Receive time out interrupt */
95#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
96#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
97
98/*
99 * These are the definitions for the Interrupt Enable Register
100 */
101#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
102#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
103#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
104#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
105
106/*
107 * These are the definitions for the Modem Control Register
108 */
109#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
110#define UART_MCR_OUT2   0x08    /* Out2 complement */
111#define UART_MCR_OUT1   0x04    /* Out1 complement */
112#define UART_MCR_RTS    0x02    /* RTS complement */
113#define UART_MCR_DTR    0x01    /* DTR complement */
114
115/*
116 * These are the definitions for the Modem Status Register
117 */
118#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
119#define UART_MSR_RI     0x40    /* Ring Indicator */
120#define UART_MSR_DSR    0x20    /* Data Set Ready */
121#define UART_MSR_CTS    0x10    /* Clear to Send */
122#define UART_MSR_DDCD   0x08    /* Delta DCD */
123#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
124#define UART_MSR_DDSR   0x02    /* Delta DSR */
125#define UART_MSR_DCTS   0x01    /* Delta CTS */
126#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
127
128/*
129 * These are the definitions for the Extended Features Register
130 * (StarTech 16C660 only, when DLAB=1)
131 */
132#define UART_EFR_CTS    0x80    /* CTS flow control */
133#define UART_EFR_RTS    0x40    /* RTS flow control */
134#define UART_EFR_SCD    0x20    /* Special character detect */
135#define UART_EFR_ENI    0x10    /* Enhanced Interrupt */
136
137#endif // __UART_H_
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