source: XOpenSparcT1/trunk/synplicity/rev_1/W1.ucf @ 31

Revision 31, 14.7 KB checked in by pntsvt00, 14 years ago (diff)

checkpoint: synthesis fail
Line 
1# Constrain per PLL (da pll_arwz.ucf )
2# Generated by Xilinx Architecture Wizard
3# --- UCF Template Only ---
4# Cut and paste these attributes into the project's UCF file, if desired
5INST PLL_INST BANDWIDTH = OPTIMIZED;
6INST PLL_INST CLKIN1_PERIOD = 5.000;
7INST PLL_INST CLKIN2_PERIOD = 10.000;
8INST PLL_INST CLKOUT0_DIVIDE = 8;
9INST PLL_INST CLKOUT0_PHASE = 0.000;
10INST PLL_INST CLKOUT0_DUTY_CYCLE = 0.500;
11INST PLL_INST COMPENSATION = SYSTEM_SYNCHRONOUS;
12INST PLL_INST DIVCLK_DIVIDE = 1;
13INST PLL_INST CLKFBOUT_MULT = 2;
14INST PLL_INST CLKFBOUT_PHASE = 0.0;
15INST PLL_INST REF_JITTER = 0.005000;
16
17
18########################## segnali globali
19
20NET  CLK_IN           LOC="K19";   # Bank 3, Vcco=2.5V, No DCI
21#### reset è negato !!!
22NET  SYSRST           LOC="E9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
23
24########################## segnali per FLASH
25NET  FLASH_ADDR<0>        LOC="K12";   # Bank 1, Vcco=3.3V
26NET  FLASH_ADDR<1>        LOC="K13";   # Bank 1, Vcco=3.3V
27NET  FLASH_ADDR<2>        LOC="H23";   # Bank 1, Vcco=3.3V
28NET  FLASH_ADDR<3>        LOC="G23";   # Bank 1, Vcco=3.3V
29NET  FLASH_ADDR<4>        LOC="H12";   # Bank 1, Vcco=3.3V
30NET  FLASH_ADDR<5>        LOC="J12";   # Bank 1, Vcco=3.3V
31NET  FLASH_ADDR<6>        LOC="K22";   # Bank 1, Vcco=3.3V
32NET  FLASH_ADDR<7>        LOC="K23";   # Bank 1, Vcco=3.3V
33NET  FLASH_ADDR<8>        LOC="K14";   # Bank 1, Vcco=3.3V
34NET  FLASH_ADDR<9>        LOC="L14";   # Bank 1, Vcco=3.3V
35NET  FLASH_ADDR<10>       LOC="H22";   # Bank 1, Vcco=3.3V
36NET  FLASH_ADDR<11>       LOC="G22";   # Bank 1, Vcco=3.3V
37NET  FLASH_ADDR<12>       LOC="J15";   # Bank 1, Vcco=3.3V
38NET  FLASH_ADDR<13>       LOC="K16";   # Bank 1, Vcco=3.3V
39NET  FLASH_ADDR<14>       LOC="K21";   # Bank 1, Vcco=3.3V
40NET  FLASH_ADDR<15>       LOC="J22";   # Bank 1, Vcco=3.3V
41NET  FLASH_ADDR<16>       LOC="L16";   # Bank 1, Vcco=3.3V
42NET  FLASH_ADDR<17>       LOC="L15";   # Bank 1, Vcco=3.3V
43NET  FLASH_ADDR<18>       LOC="L20";   # Bank 1, Vcco=3.3V
44NET  FLASH_ADDR<19>       LOC="L21";   # Bank 1, Vcco=3.3V
45NET  FLASH_ADDR<20>       LOC="AE23";  # Bank 2, Vcco=3.3V
46NET  FLASH_ADDR<21>       LOC="AE22";  # Bank 2, Vcco=3.3V
47NET  FLASH_DATA<0>        LOC="AD19";  # Bank 2, Vcco=3.3V
48NET  FLASH_DATA<1>        LOC="AE19";  # Bank 2, Vcco=3.3V
49NET  FLASH_DATA<2>        LOC="AE17";  # Bank 2, Vcco=3.3V
50NET  FLASH_DATA<3>        LOC="AF16";  # Bank 2, Vcco=3.3V
51NET  FLASH_DATA<4>        LOC="AD20";  # Bank 2, Vcco=3.3V
52NET  FLASH_DATA<5>        LOC="AE21";  # Bank 2, Vcco=3.3V
53NET  FLASH_DATA<6>        LOC="AE16";  # Bank 2, Vcco=3.3V
54NET  FLASH_DATA<7>        LOC="AF15";  # Bank 2, Vcco=3.3V
55NET  FLASH_DATA<8>        LOC="AH13";  # Bank 4, Vcco=3.3V, No DCI
56NET  FLASH_DATA<9>        LOC="AH14";  # Bank 4, Vcco=3.3V, No DCI
57NET  FLASH_DATA<10>       LOC="AH19";  # Bank 4, Vcco=3.3V, No DCI
58NET  FLASH_DATA<11>       LOC="AH20";  # Bank 4, Vcco=3.3V, No DCI
59NET  FLASH_DATA<12>       LOC="AG13";  # Bank 4, Vcco=3.3V, No DCI
60NET  FLASH_DATA<13>       LOC="AH12";  # Bank 4, Vcco=3.3V, No DCI
61NET  FLASH_DATA<14>       LOC="AH22";  # Bank 4, Vcco=3.3V, No DCI
62NET  FLASH_DATA<15>       LOC="AG22";  # Bank 4, Vcco=3.3V, No DCI
63NET  FLASH_WEN            LOC="AF20";  # Bank 2, Vcco=3.3V
64NET  FLASH_CEN            LOC="AE14";  # Bank 2, Vcco=3.3V
65NET  FLASH_CLK            LOC="N9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
66NET  FLASH_OEN            LOC="AF14";  # Bank 2, Vcco=3.3V
67#### FLASH_ADV e flash reset sono negati !!!
68NET  FLASH_ADV           LOC="F13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
69NET  FLASH_RST           LOC="AG17";  # Bank 4, Vcco=3.3V, No DCI
70
71
72########################## segnali per porta seriale
73NET  SRX      LOC="AG15";  # Bank 4, Vcco=3.3V, No DCI
74NET  STX      LOC="AG20";  # Bank 4, Vcco=3.3V, No DCI
75## mancano i segnali flash_rev
76#NET  FPGA_SERIAL2_RX      LOC="G10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
77#NET  FPGA_SERIAL2_TX      LOC="F10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
78##########################
79
80
81##################segnali per DDR
82#
83### manca phy_init_done
84NET  DDR3_CE            LOC="T28";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
85#NET  DDR3_CKE1            LOC="U30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
86NET  DDR3_CK_N          LOC="AJ29";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
87NET  DDR3_CK          LOC="AK29";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
88#NET  DDR3_CLK1_N          LOC="F28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
89#NET  DDR3_CLK1_P          LOC="E28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
90NET  DDR3_CS_N           LOC="L29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
91#NET  DDR3_CS1_B           LOC="J29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
92NET  DDR3_ODT            LOC="F31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
93#NET  DDR2_ODT<1>            LOC="F30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
94NET  DDR3_A<0>              LOC="L30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
95NET  DDR3_A<1>              LOC="M30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
96NET  DDR3_A<2>              LOC="N29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
97NET  DDR3_A<3>              LOC="P29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
98NET  DDR3_A<4>              LOC="K31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
99NET  DDR3_A<5>              LOC="L31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
100NET  DDR3_A<6>              LOC="P31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
101NET  DDR3_A<7>              LOC="P30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
102NET  DDR3_A<8>              LOC="M31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
103NET  DDR3_A<9>              LOC="R28";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
104NET  DDR3_A<10>             LOC="J31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
105NET  DDR3_A<11>             LOC="R29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
106NET  DDR3_A<12>             LOC="T31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
107# NET  DDR3_A13             LOC="H29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors     
108NET  DDR3_BA<0>             LOC="G31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
109NET  DDR3_BA<1>             LOC="J30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
110#NET  DDR3_BA<2>             LOC="R31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
111NET  DDR3_CAS_N           LOC="E31";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
112NET  DDR3_RAS_N           LOC="H30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
113NET  DDR3_WE_N            LOC="K29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
114NET  DDR3_DQ<0>              LOC="AF30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
115NET  DDR3_DQ<1>              LOC="AK31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
116NET  DDR3_DQ<2>              LOC="AF31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
117NET  DDR3_DQ<3>              LOC="AD30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
118NET  DDR3_DQ<4>              LOC="AJ30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
119NET  DDR3_DQ<5>              LOC="AF29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
120NET  DDR3_DQ<6>              LOC="AD29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
121NET  DDR3_DQ<7>              LOC="AE29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
122NET  DDR3_DQ<8>              LOC="AH27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
123NET  DDR3_DQ<9>              LOC="AF28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
124NET  DDR3_DQ<10>             LOC="AH28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
125NET  DDR3_DQ<11>             LOC="AA28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
126NET  DDR3_DQ<12>             LOC="AG25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
127NET  DDR3_DQ<13>             LOC="AJ26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
128NET  DDR3_DQ<14>             LOC="AG28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
129NET  DDR3_DQ<15>             LOC="AB28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
130NET  DDR3_DQ<16>             LOC="AC28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
131NET  DDR3_DQ<17>             LOC="AB25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
132NET  DDR3_DQ<18>             LOC="AC27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
133NET  DDR3_DQ<19>             LOC="AA26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
134NET  DDR3_DQ<20>             LOC="AB26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
135NET  DDR3_DQ<21>             LOC="AA24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
136NET  DDR3_DQ<22>             LOC="AB27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
137NET  DDR3_DQ<23>             LOC="AA25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
138NET  DDR3_DQ<24>             LOC="AC29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
139NET  DDR3_DQ<25>             LOC="AB30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
140NET  DDR3_DQ<26>             LOC="W31";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
141NET  DDR3_DQ<27>             LOC="V30";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
142NET  DDR3_DQ<28>             LOC="AC30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
143NET  DDR3_DQ<29>             LOC="W29";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
144NET  DDR3_DQ<30>             LOC="V27";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
145NET  DDR3_DQ<31>             LOC="W27";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
146NET  DDR3_DQ<32>             LOC="V29";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
147NET  DDR3_DQ<33>             LOC="Y27";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
148NET  DDR3_DQ<34>             LOC="Y26";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
149NET  DDR3_DQ<35>             LOC="W24";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
150NET  DDR3_DQ<36>             LOC="V28";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
151NET  DDR3_DQ<37>             LOC="W25";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
152NET  DDR3_DQ<38>             LOC="W26";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
153NET  DDR3_DQ<39>             LOC="V24";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
154NET  DDR3_DQ<40>             LOC="R24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
155NET  DDR3_DQ<41>             LOC="P25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
156NET  DDR3_DQ<42>             LOC="N24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
157NET  DDR3_DQ<43>             LOC="P26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
158NET  DDR3_DQ<44>             LOC="T24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
159NET  DDR3_DQ<45>             LOC="N25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
160NET  DDR3_DQ<46>             LOC="P27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
161NET  DDR3_DQ<47>             LOC="N28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
162NET  DDR3_DQ<48>             LOC="M28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
163NET  DDR3_DQ<49>             LOC="L28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
164NET  DDR3_DQ<50>             LOC="F25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
165NET  DDR3_DQ<51>             LOC="H25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
166NET  DDR3_DQ<52>             LOC="K27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
167NET  DDR3_DQ<53>             LOC="K28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
168NET  DDR3_DQ<54>             LOC="H24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
169NET  DDR3_DQ<55>             LOC="G26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
170NET  DDR3_DQ<56>             LOC="G25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
171NET  DDR3_DQ<57>             LOC="M26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
172NET  DDR3_DQ<58>             LOC="J24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
173NET  DDR3_DQ<59>             LOC="L26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
174NET  DDR3_DQ<60>             LOC="J27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
175NET  DDR3_DQ<61>             LOC="M25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
176NET  DDR3_DQ<62>             LOC="L25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
177NET  DDR3_DQ<63>             LOC="L24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
178NET  DDR3_DM<0>             LOC="AJ31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
179NET  DDR3_DM<1>             LOC="AE28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
180NET  DDR3_DM<2>             LOC="Y24";   # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
181NET  DDR3_DM<3>             LOC="Y31";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
182NET  DDR3_DM<4>             LOC="V25";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
183NET  DDR3_DM<5>             LOC="P24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
184NET  DDR3_DM<6>            LOC="F26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
185NET  DDR3_DM<7>             LOC="J25";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
186NET  DDR3_DQS_N<0>          LOC="AA30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
187NET  DDR3_DQS<0>          LOC="AA29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
188NET  DDR3_DQS_N<1>          LOC="AK27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
189NET  DDR3_DQS<1>          LOC="AK28";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
190NET  DDR3_DQS_N<2>          LOC="AJ27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
191NET  DDR3_DQS<2>         LOC="AK26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
192NET  DDR3_DQS_N<3>          LOC="AA31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
193NET  DDR3_DQS<3>         LOC="AB31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
194NET  DDR3_DQS_N<4>          LOC="Y29";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
195NET  DDR3_DQS<4>         LOC="Y28";   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
196NET  DDR3_DQS_N<5>          LOC="E27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
197NET  DDR3_DQS<5>         LOC="E26";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
198NET  DDR3_DQS_N<6>          LOC="G28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
199NET  DDR3_DQS<6>          LOC="H28";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
200NET  DDR3_DQS_N<7>          LOC="H27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
201NET  DDR3_DQS<7>         LOC="G27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
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