| Revision 9,
852 bytes
checked in by pntsvt00, 13 years ago
(diff) |
|
modifiche per la sintesi su Xilinx
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| 1 | ######################### |
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| 2 | ### DEFINE VARIABLES ### |
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| 3 | ######################### |
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| 4 | set DesignName "W1" |
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| 5 | set FamilyName "VIRTEX5" |
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| 6 | set DeviceName "XC5VLX110T" |
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| 7 | set PackageName "FF1136" |
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| 8 | set SpeedGrade "-1" |
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| 9 | set TopModule "W1" |
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| 10 | set EdifFile "W1.edf" |
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| 11 | if {![file exists $DesignName.xise]} { |
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| 12 | |
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| 13 | project new $DesignName.xise |
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| 14 | |
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| 15 | project set family $FamilyName |
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| 16 | project set device $DeviceName |
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| 17 | project set package $PackageName |
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| 18 | project set speed $SpeedGrade |
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| 19 | |
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| 20 | xfile add W1.ucf |
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| 21 | #xfile add $EdifFile |
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| 22 | #if {[file exists synplicity.ucf]} { |
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| 23 | # xfile add synplicity.ucf |
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| 24 | #} |
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| 25 | |
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| 26 | project set "Netlist Translation Type" "Timestamp" |
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| 27 | project set "Other NGDBuild Command Line Options" "-verbose" |
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| 28 | project set "Generate Detailed MAP Report" TRUE |
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| 29 | |
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| 30 | project close |
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| 31 | } |
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| 32 | |
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| 33 | |
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| 34 | file delete -force $DesignName\_xdb |
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| 35 | |
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| 36 | project open $DesignName.ise |
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| 37 | |
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| 38 | process run "Implement Design" -force rerun_all |
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| 39 | |
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| 40 | project close |
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| 41 | |
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