Changeset 22 in XOpenSparcT1 for trunk/os2wb

Timestamp:

03/31/11 12:31:26 (14 years ago)

Author:

pntsvt00

Message:

checkpoint: la DDR effettua l'init

Location:

trunk/os2wb

Files:

• os2wb.v (modified) (13 diffs)
• s1_top.v (modified) (3 diffs)

trunk/os2wb/os2wb.v

@@ -119 +119 @@
 `define PCX_REQ_CAS_COMPARE 5'b11111
 
-`define MEM_SIZE         64'h00000000_10000000
-
+//`define MEM_SIZE         64'h00000000_10000000 //256 MB
+//`define MEM_SIZE         64'h00000000_00100000  //1MB
+`define MEM_SIZE         64'h00000000_00001000  //256KB
+
+// sal: escludo test della DRAM `define TEST_DRAM        1
 `define TEST_DRAM        1
 `define DEBUGGING        1
@@ -178 +181 @@
 pcx_fifo pcx_fifo_inst( 
     .clk(clk),
-         .rst(!rstn),
+    .rst(!rstn),
     .din({pcx_atom_1,pcx_req_1,pcx_data}),
     .rd_en(fifo_rd),
     .wr_en((pcx_req_1!=5'b00000 && pcx_data[123]) || (pcx_atom_2 && pcx_data_123_d)), 
     .empty(pcx_fifo_empty),
+    .full(),
     .dout(pcx_data_fifo)
 );
@@ -209 +213 @@
    if(rstn==0)
       begin
+         //$display("INFO: OS2WB: RST_DRAM at %t",$time);
          if(`TEST_DRAM)
             state<=`TEST_DRAM_1;
          else
-            state<=`INIT_DRAM_1; // DRAM initialization is mandatory!
+         state<=`INIT_DRAM_1; // DRAM initialization is mandatory!
          cpx_ready<=0;
          fifo_rd<=0;
@@ -230 +235 @@
          `TEST_DRAM_1:
             begin
+               $display("INFO: OS2WB: TEST_DRAM_1");
                wb_cycle<=1;
                wb_strobe<=1;
@@ -239 +245 @@
             if(wb_ack)
                begin
+               $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);
                   wb_strobe<=0;
                   if(wb_addr<`MEM_SIZE-8)
@@ -258 +265 @@
          `TEST_DRAM_3:
             begin
+               $display("INFO: OS2WB: TEST_DRAM_3");
                wb_cycle<=1;
                wb_strobe<=1;
@@ -266 +274 @@
             if(wb_ack)
                begin
+                  $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time);
                   wb_strobe<=0;
                   if(wb_addr<`MEM_SIZE-8)
@@ -274 +283 @@
                               state<=`TEST_DRAM_3;
                            end
+                        else 
+                              $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time);
+
                      end
                   else
                      begin
+                        $display("INFO: OS2WB: INIT_DRAM at %t",$time);
                         state<=`INIT_DRAM_1;
                         wb_cycle<=0;
@@ -300 +313 @@
                   if(wb_addr<`MEM_SIZE-8)
                      begin
+                        //for debug 
+                        //  if (wb_addr[10:3]==8'b0) 
+                        //      $display("INFO: OS2WB: INIT_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);
+                        //
                         wb_addr[31:0]<=wb_addr[31:0]+8;
                         pcx_packet_d[64+11:64+4]<=pcx_packet_d[64+11:64+4]+1; // Address for cachedir init
@@ -306 +323 @@
                   else
                      begin
+                        $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time);
                         state<=`WAKEUP;
                         wb_cycle<=0;
@@ -349 +367 @@
                if(`DEBUGGING)
                   begin
+                     $display("INFO: OS2WB: GOT_PCX_REQ");
                      wb_sel[1:0]<=pcx_packet[113:112];
                      wb_sel[2]<=1;
@@ -1236 +1255 @@
    
    .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init),
-   .address_b({2'b01,icache_index}),
+   .address_b({2'b0,icache_index}),
    .data_b(icache_data),
    .q_b(icache1_do) 
@@ -1245 +1264 @@
    .enable(dir_en),
    .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init),
-   .address_a({1'b0,icache_index}),
+   .address_a({2'b0,icache_index}),
    .data_a(icache_data),
    .q_a(icache2_do),
    
    .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init),
-   .address_b({1'b1,icache_index}),
+   .address_b({2'b0,icache_index}),
    .data_b(icache_data),
    .q_b(icache3_do) 

trunk/os2wb/s1_top.v

@@ -140 +140 @@
     //.spc_scanout0(spc_scanout0),
     //.spc_scanout1(spc_scanout1),
-    //.tst_ctu_mbist_done(tst_ctu_mbist_done),
-    //.tst_ctu_mbist_fail(tst_ctu_mbist_fail),
-    //.spc_efc_ifuse_data(spc_efc_ifuse_data),
-    //.spc_efc_dfuse_data(spc_efc_dfuse_data),
-
-    // Wires connected to SPARC Core inputs
+    //sal:  controllare se in sintesi questi 4 segnali danno problemi!!!
+    .tst_ctu_mbist_done(),
+    .tst_ctu_mbist_fail(),
+    .spc_efc_ifuse_data(),
+    .spc_efc_dfuse_data(),
+    //
+// Wires connected to SPARC Core inputs
     .pcx_spc_grant_px(pcx_spc_grant_px),
     .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
@@ -273 +274 @@
     .fp_rdy(fp_rdy!=8'h00),
     
-    .eth_int(0/*eth_irq_i*/)
+    .eth_int(1'b0/*eth_irq_i*/)
 );
 
@@ -295 +296 @@
         .ctu_tst_short_chain(ctu_tst_short_chain),
 
-        .si(0),
+        .si(1'b0),
         .so()
 );