source:
HDLQ
@
6
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| Library | 4 | 14 years | HDLQ | ||
| TestBenches | 1 | 14 years | ttvmrc00 | upload iniziale | |
| Readme.txt | 455 bytes | 6 | 14 years | HDLQ | test permission |
This is the verilog library to simulate QCA
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