source:
HDLQ
@
1
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| Library | 1 | 14 years | ttvmrc00 | upload iniziale | |
| TestBenches | 1 | 14 years | ttvmrc00 | upload iniziale | |
| Readme.txt | 456 bytes | 1 | 14 years | ttvmrc00 | upload iniziale |
This is the verilog library to simulate QCA
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