[6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl1.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // Lowest level of lead 0 counters. Lead 0 count for 4 bits. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | module fpu_cnt_lead0_lvl1 ( |
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| 28 | din, |
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| 29 | |
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| 30 | din_3_0_eq_0, |
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| 31 | din_3_2_eq_0, |
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| 32 | lead0_4b_0 |
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| 33 | ); |
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| 34 | |
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| 35 | |
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| 36 | input [3:0] din; // data for lead 0 count bits[3:0] |
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| 37 | |
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| 38 | output din_3_0_eq_0; // data in[3:0] is zero |
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| 39 | output din_3_2_eq_0; // data in[3:2] is zero |
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| 40 | output lead0_4b_0; // bit[0] of lead 0 count |
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| 41 | |
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| 42 | |
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| 43 | wire din_3_0_eq_0; |
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| 44 | wire din_3_2_eq_0; |
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| 45 | wire lead0_4b_0; |
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| 46 | |
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| 47 | |
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| 48 | assign din_3_0_eq_0= (!(|din[3:0])); |
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| 49 | |
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| 50 | assign din_3_2_eq_0= (!(|din[3:2])); |
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| 51 | |
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| 52 | assign lead0_4b_0= ((!din_3_2_eq_0) && (!din[3])) |
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| 53 | || (din_3_2_eq_0 && (!din[1])); |
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| 54 | |
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| 55 | endmodule |
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| 56 | |
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| 57 | |
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