| 1 | //***************************************************************************** |
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| 2 | // DISCLAIMER OF LIABILITY |
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| 3 | // |
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| 4 | // This file contains proprietary and confidential information of |
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| 5 | // Xilinx, Inc. ("Xilinx"), that is distributed under a license |
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| 6 | // from Xilinx, and may be used, copied and/or disclosed only |
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| 7 | // pursuant to the terms of a valid license agreement with Xilinx. |
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| 8 | // |
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| 9 | // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION |
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| 10 | // ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER |
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| 11 | // EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT |
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| 12 | // LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, |
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| 13 | // MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx |
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| 16 | // Materials will be uninterrupted or error-free, or that defects |
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| 17 | // in the Materials will be corrected. Furthermore, Xilinx does |
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| 18 | // not warrant or make any representations regarding use, or the |
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| 19 | // results of the use, of the Materials in terms of correctness, |
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| 20 | // accuracy, reliability or otherwise. |
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| 21 | // |
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| 22 | // Xilinx products are not designed or intended to be fail-safe, |
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| 23 | // or for use in any application requiring fail-safe performance, |
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| 24 | // such as life-support or safety devices or systems, Class III |
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| 25 | // medical devices, nuclear facilities, applications related to |
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| 30 | // of any use of Xilinx products in critical applications, |
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| 31 | // subject only to applicable laws and regulations governing |
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| 32 | // limitations on product liability. |
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| 33 | // |
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| 34 | // Copyright 2006, 2007, 2008 Xilinx, Inc. |
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| 35 | // All rights reserved. |
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| 36 | // |
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| 37 | // This disclaimer and copyright notice must be retained as part |
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| 38 | // of this file at all times. |
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| 39 | //***************************************************************************** |
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| 40 | // ____ ____ |
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| 41 | // / /\/ / |
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| 42 | // /___/ \ / Vendor: Xilinx |
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| 43 | // \ \ \/ Version: 3.6 |
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| 44 | // \ \ Application: MIG |
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| 45 | // / / Filename: ddr2_mem_if_top.v |
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| 46 | // /___/ /\ Date Last Modified: $Date: 2010/06/29 12:03:43 $ |
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| 47 | // \ \ / \ Date Created: Wed Aug 16 2006 |
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| 48 | // \___\/\___\ |
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| 49 | // |
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| 50 | //Device: Virtex-5 |
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| 51 | //Design Name: DDR/DDR2 |
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| 52 | //Purpose: |
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| 53 | // Top-level for parameterizable (DDR or DDR2) memory interface |
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| 54 | //Reference: |
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| 55 | //Revision History: |
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| 56 | // Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08 |
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| 57 | // Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08 |
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| 58 | // Rev 1.3 - Parameter CS_BITS added. PK. 10/8/08 |
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| 59 | // Rev 1.4 - Parameter IODELAY_GRP added. PK. 11/27/08 |
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| 60 | //***************************************************************************** |
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| 61 | |
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| 62 | `timescale 1ns/1ps |
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| 63 | |
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| 64 | module ddr2_mem_if_top # |
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| 65 | ( |
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| 66 | // Following parameters are for 72-bit RDIMM design (for ML561 Reference |
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| 67 | // board design). Actual values may be different. Actual parameters values |
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| 68 | // are passed from design top module dram module. Please refer to |
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| 69 | // the dram module for actual values. |
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| 70 | parameter BANK_WIDTH = 2, |
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| 71 | parameter CKE_WIDTH = 1, |
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| 72 | parameter CLK_WIDTH = 1, |
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| 73 | parameter COL_WIDTH = 10, |
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| 74 | parameter CS_BITS = 0, |
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| 75 | parameter CS_NUM = 1, |
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| 76 | parameter CS_WIDTH = 1, |
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| 77 | parameter USE_DM_PORT = 1, |
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| 78 | parameter DM_WIDTH = 9, |
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| 79 | parameter DQ_WIDTH = 72, |
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| 80 | parameter DQ_BITS = 7, |
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| 81 | parameter DQ_PER_DQS = 8, |
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| 82 | parameter DQS_BITS = 4, |
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| 83 | parameter DQS_WIDTH = 9, |
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| 84 | parameter HIGH_PERFORMANCE_MODE = "TRUE", |
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| 85 | parameter IODELAY_GRP = "IODELAY_MIG", |
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| 86 | parameter ODT_WIDTH = 1, |
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| 87 | parameter ROW_WIDTH = 14, |
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| 88 | parameter APPDATA_WIDTH = 144, |
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| 89 | parameter ADDITIVE_LAT = 0, |
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| 90 | parameter BURST_LEN = 4, |
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| 91 | parameter BURST_TYPE = 0, |
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| 92 | parameter CAS_LAT = 5, |
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| 93 | parameter ECC_ENABLE = 0, |
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| 94 | parameter MULTI_BANK_EN = 1, |
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| 95 | parameter TWO_T_TIME_EN = 0, |
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| 96 | parameter ODT_TYPE = 1, |
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| 97 | parameter DDR_TYPE = 1, |
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| 98 | parameter REDUCE_DRV = 0, |
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| 99 | parameter REG_ENABLE = 1, |
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| 100 | parameter TREFI_NS = 7800, |
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| 101 | parameter TRAS = 40000, |
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| 102 | parameter TRCD = 15000, |
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| 103 | parameter TRFC = 105000, |
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| 104 | parameter TRP = 15000, |
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| 105 | parameter TRTP = 7500, |
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| 106 | parameter TWR = 15000, |
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| 107 | parameter TWTR = 10000, |
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| 108 | parameter CLK_PERIOD = 3000, |
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| 109 | parameter SIM_ONLY = 0, |
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| 110 | parameter DEBUG_EN = 0, |
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| 111 | parameter FPGA_SPEED_GRADE = 2 |
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| 112 | ) |
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| 113 | ( |
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| 114 | input clk0, |
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| 115 | input clk90, |
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| 116 | input clkdiv0, |
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| 117 | input rst0, |
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| 118 | input rst90, |
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| 119 | input rstdiv0, |
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| 120 | input [2:0] app_af_cmd, |
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| 121 | input [30:0] app_af_addr, |
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| 122 | input app_af_wren, |
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| 123 | input app_wdf_wren, |
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| 124 | input [APPDATA_WIDTH-1:0] app_wdf_data, |
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| 125 | input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data, |
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| 126 | output [1:0] rd_ecc_error, |
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| 127 | output app_af_afull, |
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| 128 | output app_wdf_afull, |
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| 129 | output rd_data_valid, |
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| 130 | output [APPDATA_WIDTH-1:0] rd_data_fifo_out, |
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| 131 | output phy_init_done, |
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| 132 | output [CLK_WIDTH-1:0] ddr_ck, |
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| 133 | output [CLK_WIDTH-1:0] ddr_ck_n, |
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| 134 | output [ROW_WIDTH-1:0] ddr_addr, |
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| 135 | output [BANK_WIDTH-1:0] ddr_ba, |
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| 136 | output ddr_ras_n, |
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| 137 | output ddr_cas_n, |
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| 138 | output ddr_we_n, |
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| 139 | output [CS_WIDTH-1:0] ddr_cs_n, |
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| 140 | output [CKE_WIDTH-1:0] ddr_cke, |
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| 141 | output [ODT_WIDTH-1:0] ddr_odt, |
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| 142 | output [DM_WIDTH-1:0] ddr_dm, |
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| 143 | inout [DQS_WIDTH-1:0] ddr_dqs, |
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| 144 | inout [DQS_WIDTH-1:0] ddr_dqs_n, |
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| 145 | inout [DQ_WIDTH-1:0] ddr_dq, |
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| 146 | // Debug signals (optional use) |
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| 147 | input dbg_idel_up_all, |
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| 148 | input dbg_idel_down_all, |
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| 149 | input dbg_idel_up_dq, |
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| 150 | input dbg_idel_down_dq, |
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| 151 | input dbg_idel_up_dqs, |
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| 152 | input dbg_idel_down_dqs, |
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| 153 | input dbg_idel_up_gate, |
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| 154 | input dbg_idel_down_gate, |
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| 155 | input [DQ_BITS-1:0] dbg_sel_idel_dq, |
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| 156 | input dbg_sel_all_idel_dq, |
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| 157 | input [DQS_BITS:0] dbg_sel_idel_dqs, |
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| 158 | input dbg_sel_all_idel_dqs, |
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| 159 | input [DQS_BITS:0] dbg_sel_idel_gate, |
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| 160 | input dbg_sel_all_idel_gate, |
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| 161 | output [3:0] dbg_calib_done, |
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| 162 | output [3:0] dbg_calib_err, |
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| 163 | output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt, |
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| 164 | output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt, |
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| 165 | output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt, |
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| 166 | output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel, |
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| 167 | output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly, |
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| 168 | output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly |
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| 169 | ); |
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| 170 | |
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| 171 | wire [30:0] af_addr; |
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| 172 | wire [2:0] af_cmd; |
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| 173 | wire af_empty; |
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| 174 | wire [ROW_WIDTH-1:0] ctrl_addr; |
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| 175 | wire ctrl_af_rden; |
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| 176 | wire [BANK_WIDTH-1:0] ctrl_ba; |
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| 177 | wire ctrl_cas_n; |
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| 178 | wire [CS_NUM-1:0] ctrl_cs_n; |
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| 179 | wire ctrl_ras_n; |
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| 180 | wire ctrl_rden; |
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| 181 | wire ctrl_ref_flag; |
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| 182 | wire ctrl_we_n; |
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| 183 | wire ctrl_wren; |
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| 184 | wire [DQS_WIDTH-1:0] phy_calib_rden; |
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| 185 | wire [DQS_WIDTH-1:0] phy_calib_rden_sel; |
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| 186 | wire [DQ_WIDTH-1:0] rd_data_fall; |
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| 187 | wire [DQ_WIDTH-1:0] rd_data_rise; |
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| 188 | wire [(2*DQ_WIDTH)-1:0] wdf_data; |
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| 189 | wire [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data; |
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| 190 | wire wdf_rden; |
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| 191 | |
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| 192 | //*************************************************************************** |
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| 193 | |
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| 194 | ddr2_phy_top # |
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| 195 | ( |
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| 196 | .BANK_WIDTH (BANK_WIDTH), |
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| 197 | .CKE_WIDTH (CKE_WIDTH), |
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| 198 | .CLK_WIDTH (CLK_WIDTH), |
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| 199 | .COL_WIDTH (COL_WIDTH), |
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| 200 | .CS_BITS (CS_BITS), |
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| 201 | .CS_NUM (CS_NUM), |
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| 202 | .CS_WIDTH (CS_WIDTH), |
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| 203 | .USE_DM_PORT (USE_DM_PORT), |
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| 204 | .DM_WIDTH (DM_WIDTH), |
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| 205 | .DQ_WIDTH (DQ_WIDTH), |
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| 206 | .DQ_BITS (DQ_BITS), |
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| 207 | .DQ_PER_DQS (DQ_PER_DQS), |
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| 208 | .DQS_BITS (DQS_BITS), |
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| 209 | .DQS_WIDTH (DQS_WIDTH), |
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| 210 | .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), |
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| 211 | .IODELAY_GRP (IODELAY_GRP), |
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| 212 | .ODT_WIDTH (ODT_WIDTH), |
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| 213 | .ROW_WIDTH (ROW_WIDTH), |
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| 214 | .TWO_T_TIME_EN (TWO_T_TIME_EN), |
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| 215 | .ADDITIVE_LAT (ADDITIVE_LAT), |
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| 216 | .BURST_LEN (BURST_LEN), |
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| 217 | .BURST_TYPE (BURST_TYPE), |
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| 218 | .CAS_LAT (CAS_LAT), |
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| 219 | .ECC_ENABLE (ECC_ENABLE), |
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| 220 | .ODT_TYPE (ODT_TYPE), |
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| 221 | .DDR_TYPE (DDR_TYPE), |
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| 222 | .REDUCE_DRV (REDUCE_DRV), |
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| 223 | .REG_ENABLE (REG_ENABLE), |
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| 224 | .TWR (TWR), |
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| 225 | .CLK_PERIOD (CLK_PERIOD), |
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| 226 | .SIM_ONLY (SIM_ONLY), |
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| 227 | .DEBUG_EN (DEBUG_EN), |
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| 228 | .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE) |
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| 229 | ) |
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| 230 | u_phy_top |
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| 231 | ( |
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| 232 | .clk0 (clk0), |
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| 233 | .clk90 (clk90), |
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| 234 | .clkdiv0 (clkdiv0), |
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| 235 | .rst0 (rst0), |
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| 236 | .rst90 (rst90), |
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| 237 | .rstdiv0 (rstdiv0), |
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| 238 | .ctrl_wren (ctrl_wren), |
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| 239 | .ctrl_addr (ctrl_addr), |
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| 240 | .ctrl_ba (ctrl_ba), |
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| 241 | .ctrl_ras_n (ctrl_ras_n), |
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| 242 | .ctrl_cas_n (ctrl_cas_n), |
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| 243 | .ctrl_we_n (ctrl_we_n), |
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| 244 | .ctrl_cs_n (ctrl_cs_n), |
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| 245 | .ctrl_rden (ctrl_rden), |
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| 246 | .ctrl_ref_flag (ctrl_ref_flag), |
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| 247 | .wdf_data (wdf_data), |
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| 248 | .wdf_mask_data (wdf_mask_data), |
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| 249 | .wdf_rden (wdf_rden), |
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| 250 | .phy_init_done (phy_init_done), |
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| 251 | .phy_calib_rden (phy_calib_rden), |
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| 252 | .phy_calib_rden_sel (phy_calib_rden_sel), |
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| 253 | .rd_data_rise (rd_data_rise), |
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| 254 | .rd_data_fall (rd_data_fall), |
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| 255 | .ddr_ck (ddr_ck), |
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| 256 | .ddr_ck_n (ddr_ck_n), |
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| 257 | .ddr_addr (ddr_addr), |
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| 258 | .ddr_ba (ddr_ba), |
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| 259 | .ddr_ras_n (ddr_ras_n), |
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| 260 | .ddr_cas_n (ddr_cas_n), |
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| 261 | .ddr_we_n (ddr_we_n), |
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| 262 | .ddr_cs_n (ddr_cs_n), |
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| 263 | .ddr_cke (ddr_cke), |
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| 264 | .ddr_odt (ddr_odt), |
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| 265 | .ddr_dm (ddr_dm), |
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| 266 | .ddr_dqs (ddr_dqs), |
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| 267 | .ddr_dqs_n (ddr_dqs_n), |
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| 268 | .ddr_dq (ddr_dq), |
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| 269 | .dbg_idel_up_all (dbg_idel_up_all), |
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| 270 | .dbg_idel_down_all (dbg_idel_down_all), |
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| 271 | .dbg_idel_up_dq (dbg_idel_up_dq), |
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| 272 | .dbg_idel_down_dq (dbg_idel_down_dq), |
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| 273 | .dbg_idel_up_dqs (dbg_idel_up_dqs), |
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| 274 | .dbg_idel_down_dqs (dbg_idel_down_dqs), |
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| 275 | .dbg_idel_up_gate (dbg_idel_up_gate), |
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| 276 | .dbg_idel_down_gate (dbg_idel_down_gate), |
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| 277 | .dbg_sel_idel_dq (dbg_sel_idel_dq), |
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| 278 | .dbg_sel_all_idel_dq (dbg_sel_all_idel_dq), |
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| 279 | .dbg_sel_idel_dqs (dbg_sel_idel_dqs), |
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| 280 | .dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs), |
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| 281 | .dbg_sel_idel_gate (dbg_sel_idel_gate), |
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| 282 | .dbg_sel_all_idel_gate (dbg_sel_all_idel_gate), |
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| 283 | .dbg_calib_done (dbg_calib_done), |
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| 284 | .dbg_calib_err (dbg_calib_err), |
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| 285 | .dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt), |
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| 286 | .dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt), |
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| 287 | .dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt), |
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| 288 | .dbg_calib_rd_data_sel (dbg_calib_rd_data_sel), |
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| 289 | .dbg_calib_rden_dly (dbg_calib_rden_dly), |
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| 290 | .dbg_calib_gate_dly (dbg_calib_gate_dly) |
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| 291 | ); |
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| 292 | |
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| 293 | ddr2_usr_top # |
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| 294 | ( |
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| 295 | .BANK_WIDTH (BANK_WIDTH), |
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| 296 | .COL_WIDTH (COL_WIDTH), |
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| 297 | .CS_BITS (CS_BITS), |
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| 298 | .DQ_WIDTH (DQ_WIDTH), |
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| 299 | .DQ_PER_DQS (DQ_PER_DQS), |
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| 300 | .DQS_WIDTH (DQS_WIDTH), |
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| 301 | .APPDATA_WIDTH (APPDATA_WIDTH), |
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| 302 | .ECC_ENABLE (ECC_ENABLE), |
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| 303 | .ROW_WIDTH (ROW_WIDTH) |
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| 304 | ) |
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| 305 | u_usr_top |
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| 306 | ( |
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| 307 | .clk0 (clk0), |
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| 308 | .clk90 (clk90), |
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| 309 | .rst0 (rst0), |
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| 310 | .rd_data_in_rise (rd_data_rise), |
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| 311 | .rd_data_in_fall (rd_data_fall), |
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| 312 | .phy_calib_rden (phy_calib_rden), |
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| 313 | .phy_calib_rden_sel(phy_calib_rden_sel), |
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| 314 | .rd_data_valid (rd_data_valid), |
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| 315 | .rd_ecc_error (rd_ecc_error), |
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| 316 | .rd_data_fifo_out (rd_data_fifo_out), |
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| 317 | .app_af_cmd (app_af_cmd), |
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| 318 | .app_af_addr (app_af_addr), |
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| 319 | .app_af_wren (app_af_wren), |
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| 320 | .ctrl_af_rden (ctrl_af_rden), |
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| 321 | .af_cmd (af_cmd), |
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| 322 | .af_addr (af_addr), |
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| 323 | .af_empty (af_empty), |
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| 324 | .app_af_afull (app_af_afull), |
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| 325 | .app_wdf_wren (app_wdf_wren), |
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| 326 | .app_wdf_data (app_wdf_data), |
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| 327 | .app_wdf_mask_data (app_wdf_mask_data), |
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| 328 | .wdf_rden (wdf_rden), |
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| 329 | .app_wdf_afull (app_wdf_afull), |
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| 330 | .wdf_data (wdf_data), |
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| 331 | .wdf_mask_data (wdf_mask_data) |
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| 332 | ); |
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| 333 | |
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| 334 | |
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| 335 | ddr2_ctrl # |
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| 336 | ( |
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| 337 | .BANK_WIDTH (BANK_WIDTH), |
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| 338 | .COL_WIDTH (COL_WIDTH), |
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| 339 | .CS_BITS (CS_BITS), |
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| 340 | .CS_NUM (CS_NUM), |
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| 341 | .ROW_WIDTH (ROW_WIDTH), |
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| 342 | .ADDITIVE_LAT (ADDITIVE_LAT), |
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| 343 | .BURST_LEN (BURST_LEN), |
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| 344 | .CAS_LAT (CAS_LAT), |
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| 345 | .ECC_ENABLE (ECC_ENABLE), |
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| 346 | .REG_ENABLE (REG_ENABLE), |
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| 347 | .MULTI_BANK_EN (MULTI_BANK_EN), |
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| 348 | .TWO_T_TIME_EN (TWO_T_TIME_EN), |
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| 349 | .TREFI_NS (TREFI_NS), |
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| 350 | .TRAS (TRAS), |
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| 351 | .TRCD (TRCD), |
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| 352 | .TRFC (TRFC), |
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| 353 | .TRP (TRP), |
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| 354 | .TRTP (TRTP), |
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| 355 | .TWR (TWR), |
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| 356 | .TWTR (TWTR), |
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| 357 | .CLK_PERIOD (CLK_PERIOD), |
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| 358 | .DDR_TYPE (DDR_TYPE) |
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| 359 | ) |
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| 360 | u_ctrl |
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| 361 | ( |
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| 362 | .clk (clk0), |
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| 363 | .rst (rst0), |
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| 364 | .af_cmd (af_cmd), |
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| 365 | .af_addr (af_addr), |
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| 366 | .af_empty (af_empty), |
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| 367 | .phy_init_done (phy_init_done), |
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| 368 | .ctrl_ref_flag (ctrl_ref_flag), |
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| 369 | .ctrl_af_rden (ctrl_af_rden), |
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| 370 | .ctrl_wren (ctrl_wren), |
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| 371 | .ctrl_rden (ctrl_rden), |
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| 372 | .ctrl_addr (ctrl_addr), |
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| 373 | .ctrl_ba (ctrl_ba), |
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| 374 | .ctrl_ras_n (ctrl_ras_n), |
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| 375 | .ctrl_cas_n (ctrl_cas_n), |
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| 376 | .ctrl_we_n (ctrl_we_n), |
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| 377 | .ctrl_cs_n (ctrl_cs_n) |
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| 378 | ); |
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| 379 | |
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| 380 | endmodule |
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