| [6] | 1 | ############################################################## |
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| 2 | ############################################################## |
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| 3 | ############################################################## |
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| 4 | SET designentry = Verilog |
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| 5 | SET BusFormat = BusFormatAngleBracketNotRipped |
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| 6 | SET devicefamily = virtex5 |
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| 7 | SET device = xc5vlx110t |
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| 8 | SET package = ff1136 |
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| 9 | SET speedgrade = -3 |
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| 10 | SET FlowVendor = Foundation_ISE |
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| 11 | SET VerilogSim = True |
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| 12 | SET VHDLSim = True |
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| 13 | SELECT Fifo_Generator family Xilinx,_Inc. 6.2 |
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| 14 | CSET almost_empty_flag=false |
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| 15 | CSET almost_full_flag=false |
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| 16 | CSET component_name=dram_fifo |
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| 17 | CSET data_count=false |
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| 18 | CSET data_count_width=10 |
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| 19 | CSET disable_timing_violations=false |
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| 20 | CSET dout_reset_value=0 |
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| 21 | CSET empty_threshold_assert_value=2 |
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| 22 | CSET empty_threshold_negate_value=3 |
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| 23 | CSET enable_ecc=false |
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| 24 | CSET enable_int_clk=false |
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| 25 | CSET enable_reset_synchronization=true |
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| 26 | CSET fifo_implementation=Independent_Clocks_Block_RAM |
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| 27 | CSET full_flags_reset_value=1 |
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| 28 | CSET full_threshold_assert_value=1021 |
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| 29 | CSET full_threshold_negate_value=1020 |
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| 30 | CSET inject_dbit_error=false |
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| 31 | CSET inject_sbit_error=false |
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| 32 | CSET input_data_width=104 |
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| 33 | CSET input_depth=1024 |
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| 34 | CSET output_data_width=104 |
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| 35 | CSET output_depth=1024 |
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| 36 | CSET overflow_flag=false |
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| 37 | CSET overflow_sense=Active_High |
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| 38 | CSET performance_options=Standard_FIFO |
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| 39 | CSET programmable_empty_type=No_Programmable_Empty_Threshold |
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| 40 | CSET programmable_full_type=No_Programmable_Full_Threshold |
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| 41 | CSET read_clock_frequency=1 |
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| 42 | CSET read_data_count=false |
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| 43 | CSET read_data_count_width=10 |
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| 44 | CSET reset_pin=true |
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| 45 | CSET reset_type=Asynchronous_Reset |
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| 46 | CSET underflow_flag=false |
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| 47 | CSET underflow_sense=Active_High |
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| 48 | CSET use_dout_reset=true |
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| 49 | CSET use_embedded_registers=false |
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| 50 | CSET use_extra_logic=false |
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| 51 | CSET valid_flag=false |
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| 52 | CSET valid_sense=Active_High |
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| 53 | CSET write_acknowledge_flag=false |
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| 54 | CSET write_acknowledge_sense=Active_High |
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| 55 | CSET write_clock_frequency=1 |
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| 56 | CSET write_data_count=true |
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| 57 | CSET write_data_count_width=8 |
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| 58 | GENERATE |
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