| 1 | NET AUDIO_BIT_CLK LOC="AF18"; # Bank 4, Vcco=3.3V, No DCI |
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| 2 | NET AUDIO_SDATA_IN LOC="AE18"; # Bank 4, Vcco=3.3V, No DCI |
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| 3 | NET AUDIO_SDATA_OUT LOC="AG16"; # Bank 4, Vcco=3.3V, No DCI |
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| 4 | NET AUDIO_SYNC LOC="AF19"; # Bank 4, Vcco=3.3V, No DCI |
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| 5 | NET BUS_ERROR_1 LOC="F6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 6 | NET BUS_ERROR_2 LOC="T10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 7 | NET CFG_ADDR_OUT0 LOC="AE12"; # Bank 2, Vcco=3.3V |
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| 8 | NET CFG_ADDR_OUT1 LOC="AE13"; # Bank 2, Vcco=3.3V |
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| 9 | NET CLK_27MHZ_FPGA LOC="AG18"; # Bank 4, Vcco=3.3V, No DCI |
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| 10 | NET CLK_33MHZ_FPGA LOC="AH17"; # Bank 4, Vcco=3.3V, No DCI |
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| 11 | NET CLK_FPGA_N LOC="K19"; # Bank 3, Vcco=2.5V, No DCI |
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| 12 | NET CLK_FPGA_P LOC="L19"; # Bank 3, Vcco=2.5V, No DCI |
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| 13 | NET CLKBUF_Q0_N LOC="H3"; # Bank 116, MGTREFCLKN_116, GTP_DUAL_X0Y4 |
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| 14 | NET CLKBUF_Q0_P LOC="H4"; # Bank 116, MGTREFCLKP_116, GTP_DUAL_X0Y4 |
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| 15 | NET CLKBUF_Q1_N LOC="J19"; # Bank 3, Vcco=2.5V, No DCI |
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| 16 | NET CLKBUF_Q1_P LOC="K18"; # Bank 3, Vcco=2.5V, No DCI |
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| 17 | NET CPLD_IO_1 LOC="W10"; # Bank 18, Vcco=3.3V, No DCI |
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| 18 | NET CPU_TCK LOC="E6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 19 | NET CPU_TDO LOC="E7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 20 | NET CPU_TMS LOC="U10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 21 | NET CPU_TRST LOC="V10"; # Bank 18, Vcco=3.3V, No DCI |
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| 22 | NET DDR2_A0 LOC="L30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 23 | NET DDR2_A1 LOC="M30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 24 | NET DDR2_A2 LOC="N29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 25 | NET DDR2_A3 LOC="P29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 26 | NET DDR2_A4 LOC="K31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 27 | NET DDR2_A5 LOC="L31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 28 | NET DDR2_A6 LOC="P31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 29 | NET DDR2_A7 LOC="P30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 30 | NET DDR2_A8 LOC="M31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 31 | NET DDR2_A9 LOC="R28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 32 | NET DDR2_A10 LOC="J31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 33 | NET DDR2_A11 LOC="R29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 34 | NET DDR2_A12 LOC="T31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 35 | NET DDR2_A13 LOC="H29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 36 | NET DDR2_BA0 LOC="G31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 37 | NET DDR2_BA1 LOC="J30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 38 | NET DDR2_BA2 LOC="R31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 39 | NET DDR2_CAS_B LOC="E31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 40 | NET DDR2_CKE0 LOC="T28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 41 | NET DDR2_CKE1 LOC="U30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 42 | NET DDR2_CLK0_N LOC="AJ29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 43 | NET DDR2_CLK0_P LOC="AK29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 44 | NET DDR2_CLK1_N LOC="F28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 45 | NET DDR2_CLK1_P LOC="E28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 46 | NET DDR2_CS0_B LOC="L29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 47 | NET DDR2_CS1_B LOC="J29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 48 | NET DDR2_D0 LOC="AF30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 49 | NET DDR2_D1 LOC="AK31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 50 | NET DDR2_D2 LOC="AF31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 51 | NET DDR2_D3 LOC="AD30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 52 | NET DDR2_D4 LOC="AJ30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 53 | NET DDR2_D5 LOC="AF29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 54 | NET DDR2_D6 LOC="AD29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 55 | NET DDR2_D7 LOC="AE29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 56 | NET DDR2_D8 LOC="AH27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 57 | NET DDR2_D9 LOC="AF28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 58 | NET DDR2_D10 LOC="AH28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 59 | NET DDR2_D11 LOC="AA28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 60 | NET DDR2_D12 LOC="AG25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 61 | NET DDR2_D13 LOC="AJ26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 62 | NET DDR2_D14 LOC="AG28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 63 | NET DDR2_D15 LOC="AB28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 64 | NET DDR2_D16 LOC="AC28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 65 | NET DDR2_D17 LOC="AB25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 66 | NET DDR2_D18 LOC="AC27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 67 | NET DDR2_D19 LOC="AA26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 68 | NET DDR2_D20 LOC="AB26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 69 | NET DDR2_D21 LOC="AA24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 70 | NET DDR2_D22 LOC="AB27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 71 | NET DDR2_D23 LOC="AA25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 72 | NET DDR2_D24 LOC="AC29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 73 | NET DDR2_D25 LOC="AB30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 74 | NET DDR2_D26 LOC="W31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 75 | NET DDR2_D27 LOC="V30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 76 | NET DDR2_D28 LOC="AC30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 77 | NET DDR2_D29 LOC="W29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 78 | NET DDR2_D30 LOC="V27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 79 | NET DDR2_D31 LOC="W27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 80 | NET DDR2_D32 LOC="V29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 81 | NET DDR2_D33 LOC="Y27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 82 | NET DDR2_D34 LOC="Y26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 83 | NET DDR2_D35 LOC="W24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 84 | NET DDR2_D36 LOC="V28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 85 | NET DDR2_D37 LOC="W25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 86 | NET DDR2_D38 LOC="W26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 87 | NET DDR2_D39 LOC="V24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 88 | NET DDR2_D40 LOC="R24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 89 | NET DDR2_D41 LOC="P25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 90 | NET DDR2_D42 LOC="N24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 91 | NET DDR2_D43 LOC="P26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 92 | NET DDR2_D44 LOC="T24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 93 | NET DDR2_D45 LOC="N25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 94 | NET DDR2_D46 LOC="P27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 95 | NET DDR2_D47 LOC="N28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 96 | NET DDR2_D48 LOC="M28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 97 | NET DDR2_D49 LOC="L28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 98 | NET DDR2_D50 LOC="F25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 99 | NET DDR2_D51 LOC="H25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 100 | NET DDR2_D52 LOC="K27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 101 | NET DDR2_D53 LOC="K28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 102 | NET DDR2_D54 LOC="H24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 103 | NET DDR2_D55 LOC="G26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 104 | NET DDR2_D56 LOC="G25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 105 | NET DDR2_D57 LOC="M26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 106 | NET DDR2_D58 LOC="J24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 107 | NET DDR2_D59 LOC="L26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 108 | NET DDR2_D60 LOC="J27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 109 | NET DDR2_D61 LOC="M25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 110 | NET DDR2_D62 LOC="L25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 111 | NET DDR2_D63 LOC="L24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 112 | NET DDR2_DM0 LOC="AJ31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 113 | NET DDR2_DM1 LOC="AE28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 114 | NET DDR2_DM2 LOC="Y24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 115 | NET DDR2_DM3 LOC="Y31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 116 | NET DDR2_DM4 LOC="V25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 117 | NET DDR2_DM5 LOC="P24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 118 | NET DDR2_DM6 LOC="F26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 119 | NET DDR2_DM7 LOC="J25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 120 | NET DDR2_DQS0_N LOC="AA30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 121 | NET DDR2_DQS0_P LOC="AA29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 122 | NET DDR2_DQS1_N LOC="AK27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 123 | NET DDR2_DQS1_P LOC="AK28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 124 | NET DDR2_DQS2_N LOC="AJ27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 125 | NET DDR2_DQS2_P LOC="AK26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 126 | NET DDR2_DQS3_N LOC="AA31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 127 | NET DDR2_DQS3_P LOC="AB31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 128 | NET DDR2_DQS4_N LOC="Y29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 129 | NET DDR2_DQS4_P LOC="Y28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 130 | NET DDR2_DQS5_N LOC="E27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 131 | NET DDR2_DQS5_P LOC="E26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 132 | NET DDR2_DQS6_N LOC="G28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 133 | NET DDR2_DQS6_P LOC="H28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 134 | NET DDR2_DQS7_N LOC="H27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 135 | NET DDR2_DQS7_P LOC="G27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 136 | NET DDR2_ODT0 LOC="F31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 137 | NET DDR2_ODT1 LOC="F30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 138 | NET DDR2_RAS_B LOC="H30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 139 | NET DDR2_SCL LOC="E29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 140 | NET DDR2_SDA LOC="F29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 141 | NET DDR2_WE_B LOC="K29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 142 | NET DVI_D0 LOC="AB8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 143 | NET DVI_D1 LOC="AC8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 144 | NET DVI_D2 LOC="AN12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 145 | NET DVI_D3 LOC="AP12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 146 | NET DVI_D4 LOC="AA9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 147 | NET DVI_D5 LOC="AA8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 148 | NET DVI_D6 LOC="AM13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 149 | NET DVI_D7 LOC="AN13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 150 | NET DVI_D8 LOC="AA10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 151 | NET DVI_D9 LOC="AB10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 152 | NET DVI_D10 LOC="AP14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 153 | NET DVI_D11 LOC="AN14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 154 | NET DVI_DE LOC="AE8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 155 | NET DVI_GPIO1 LOC="N30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 156 | NET DVI_H LOC="AM12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 157 | NET DVI_RESET_B LOC="AK6"; # Bank 18, Vcco=3.3V, No DCI |
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| 158 | NET DVI_V LOC="AM11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 159 | NET DVI_XCLK_N LOC="AL10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 160 | NET DVI_XCLK_P LOC="AL11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 161 | NET FAN_ALERT_B LOC="T30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 162 | NET FLASH_ADV_B LOC="F13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 163 | NET FLASH_AUDIO_RESET_B LOC="AG17"; # Bank 4, Vcco=3.3V, No DCI |
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| 164 | NET FLASH_CE_B LOC="AE14"; # Bank 2, Vcco=3.3V |
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| 165 | NET FLASH_CLK LOC="N9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 166 | NET FLASH_OE_B LOC="AF14"; # Bank 2, Vcco=3.3V |
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| 167 | NET FLASH_WAIT LOC="G13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 168 | NET FPGA_AVDD LOC="T18"; # Bank 0, Vcco=3.3V |
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| 169 | NET FPGA_CCLK-R LOC="N15"; # Bank 0, Vcco=3.3V |
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| 170 | NET FPGA_CPU_RESET_B LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 171 | NET FPGA_CS_B LOC="N22"; # Bank 0, Vcco=3.3V |
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| 172 | NET FPGA_CS0_B LOC="AF21"; # Bank 2, Vcco=3.3V |
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| 173 | NET FPGA_DIFF_CLK_OUT_N LOC="J21"; # Bank 3, Vcco=2.5V, No DCI |
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| 174 | NET FPGA_DIFF_CLK_OUT_P LOC="J20"; # Bank 3, Vcco=2.5V, No DCI |
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| 175 | NET FPGA_DIN LOC="P15"; # Bank 0, Vcco=3.3V |
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| 176 | NET FPGA_DONE LOC="M15"; # Bank 0, Vcco=3.3V |
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| 177 | NET FPGA_DOUT_BUSY LOC="AD15"; # Bank 0, Vcco=3.3V |
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| 178 | NET FPGA_DX_N LOC="W17"; # Bank 0, Vcco=3.3V |
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| 179 | NET FPGA_DX_P LOC="W18"; # Bank 0, Vcco=3.3V |
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| 180 | NET FPGA_EXP_TCK LOC="AB15"; # Bank 0, Vcco=3.3V |
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| 181 | NET FPGA_EXP_TMS LOC="AC14"; # Bank 0, Vcco=3.3V |
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| 182 | NET FPGA_HSWAPEN LOC="M23"; # Bank 0, Vcco=3.3V |
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| 183 | NET FPGA_INIT_B LOC="N14"; # Bank 0, Vcco=3.3V |
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| 184 | NET FPGA_M0 LOC="AD21"; # Bank 0, Vcco=3.3V |
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| 185 | NET FPGA_M1 LOC="AC22"; # Bank 0, Vcco=3.3V |
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| 186 | NET FPGA_M2 LOC="AD22"; # Bank 0, Vcco=3.3V |
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| 187 | NET FPGA_PROG_B LOC="M22"; # Bank 0, Vcco=3.3V |
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| 188 | NET FPGA_RDWR_B LOC="N23"; # Bank 0, Vcco=3.3V |
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| 189 | NET FPGA_ROTARY_INCA LOC="AH30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 190 | NET FPGA_ROTARY_INCB LOC="AG30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 191 | NET FPGA_ROTARY_PUSH LOC="AH29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
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| 192 | NET FPGA_SERIAL1_RX LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI |
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| 193 | NET FPGA_SERIAL1_TX LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI |
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| 194 | NET FPGA_SERIAL2_RX LOC="G10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
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| 195 | NET FPGA_SERIAL2_TX LOC="F10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 196 | NET FPGA_TDI LOC="AC15"; # Bank 0, Vcco=3.3V |
|---|
| 197 | NET FPGA_TDO LOC="AD14"; # Bank 0, Vcco=3.3V |
|---|
| 198 | NET FPGA_V_N LOC="V17"; # Bank 0, Vcco=3.3V (SYSMON External Input: VN) J9-10 |
|---|
| 199 | NET FPGA_V_P LOC="U18"; # Bank 0, Vcco=3.3V (SYSMON External Input: VP) J9-9 |
|---|
| 200 | NET FPGA_VBATT LOC="L23"; # Bank 0, Vcco=3.3V |
|---|
| 201 | NET FPGA_VREFP LOC="V18"; # Bank 0, Vcco=3.3V |
|---|
| 202 | NET FPGA_VRN_B11 LOC="N33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 203 | NET FPGA_VRN_B13 LOC="AG33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 204 | NET FPGA_VRN_B17 LOC="AD31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 205 | NET FPGA_VRN_B19 LOC="N27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 206 | NET FPGA_VRN_B20 LOC="L10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 207 | NET FPGA_VRN_B21 LOC="AJ25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 208 | NET FPGA_VRN_B22 LOC="AF8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 209 | NET FPGA_VRP_B11 LOC="M33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 210 | NET FPGA_VRP_B13 LOC="AH33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 211 | NET FPGA_VRP_B17 LOC="AE31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 212 | NET FPGA_VRP_B19 LOC="M27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 213 | NET FPGA_VRP_B20 LOC="L11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 214 | NET FPGA_VRP_B21 LOC="AH25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 215 | NET FPGA_VRP_B22 LOC="AE9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 216 | NET GPIO_DIP_SW1 LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 217 | NET GPIO_DIP_SW2 LOC="AG27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 218 | NET GPIO_DIP_SW3 LOC="AF25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 219 | NET GPIO_DIP_SW4 LOC="AF26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 220 | NET GPIO_DIP_SW5 LOC="AE27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 221 | NET GPIO_DIP_SW6 LOC="AE26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 222 | NET GPIO_DIP_SW7 LOC="AC25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 223 | NET GPIO_DIP_SW8 LOC="AC24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 224 | NET GPIO_LED_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 225 | NET GPIO_LED_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 226 | NET GPIO_LED_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 227 | NET GPIO_LED_3 LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 228 | NET GPIO_LED_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 229 | NET GPIO_LED_5 LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 230 | NET GPIO_LED_6 LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 231 | NET GPIO_LED_7 LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 232 | NET GPIO_LED_C LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 233 | NET GPIO_LED_E LOC="AG23"; # Bank 2, Vcco=3.3V |
|---|
| 234 | NET GPIO_LED_N LOC="AF13"; # Bank 2, Vcco=3.3V |
|---|
| 235 | NET GPIO_LED_S LOC="AG12"; # Bank 2, Vcco=3.3V |
|---|
| 236 | NET GPIO_LED_W LOC="AF23"; # Bank 2, Vcco=3.3V |
|---|
| 237 | NET GPIO_SW_C LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 238 | NET GPIO_SW_E LOC="AK7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 239 | NET GPIO_SW_N LOC="U8"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 240 | NET GPIO_SW_S LOC="V8"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 241 | NET GPIO_SW_W LOC="AJ7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 242 | NET HDR1_2 LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 243 | NET HDR1_4 LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 244 | NET HDR1_6 LOC="H34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 245 | NET HDR1_8 LOC="G33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 246 | NET HDR1_10 LOC="G32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 247 | NET HDR1_12 LOC="H32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 248 | NET HDR1_14 LOC="J32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 249 | NET HDR1_16 LOC="J34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 250 | NET HDR1_18 LOC ="L33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 251 | NET HDR1_20 LOC="M32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 252 | NET HDR1_22 LOC="P34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 253 | NET HDR1_24 LOC="N34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 254 | NET HDR1_26 LOC="AA34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[5]) J6-26 |
|---|
| 255 | NET HDR1_28 LOC="AD32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 256 | NET HDR1_30 LOC="Y34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[5]) J6-30 |
|---|
| 257 | NET HDR1_32 LOC="Y32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 258 | NET HDR1_34 LOC="W32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 259 | NET HDR1_36 LOC="AH34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 260 | NET HDR1_38 LOC="AE32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 261 | NET HDR1_40 LOC="AG32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 262 | NET HDR1_42 LOC="AH32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 263 | NET HDR1_44 LOC="AK34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 264 | NET HDR1_46 LOC="AK33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 265 | NET HDR1_48 LOC="AJ32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 266 | NET HDR1_50 LOC="AK32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 267 | NET HDR1_52 LOC="AL34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 268 | NET HDR1_54 LOC="AL33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 269 | NET HDR1_56 LOC="AM33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 270 | NET HDR1_58 LOC="AJ34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 271 | NET HDR1_60 LOC="AM32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 272 | NET HDR1_62 LOC="AN34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 273 | NET HDR1_64 LOC="AN33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 274 | NET HDR2_2_SM_8_N LOC="K34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[15]) J4-2 |
|---|
| 275 | NET HDR2_4_SM_8_P LOC="L34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[15]) J4-4 |
|---|
| 276 | NET HDR2_6_SM_7_N LOC="K32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[14]) J4-6 |
|---|
| 277 | NET HDR2_8_SM_7_P LOC="K33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[14]) J4-8 |
|---|
| 278 | NET HDR2_10_DIFF_0_N LOC="N32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[13]) J4-10 |
|---|
| 279 | NET HDR2_12_DIFF_0_P LOC="P32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[13]) J4-12 |
|---|
| 280 | NET HDR2_14_DIFF_1_N LOC="R34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[12]) J4-14 |
|---|
| 281 | NET HDR2_16_DIFF_1_P LOC="T33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[12]) J4-16 |
|---|
| 282 | NET HDR2_18_DIFF_2_N LOC="R32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[11]) J4-18 |
|---|
| 283 | NET HDR2_20_DIFF_2_P LOC="R33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[11]) J4-20 |
|---|
| 284 | NET HDR2_22_SM_10_N LOC="T34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[10]) J4-22 |
|---|
| 285 | NET HDR2_24_SM_10_P LOC="U33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[10]) J4-24 |
|---|
| 286 | NET HDR2_26_SM_11_N LOC="U31"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[9]) J4-26 |
|---|
| 287 | NET HDR2_28_SM_11_P LOC="U32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[9]) J4-28 |
|---|
| 288 | NET HDR2_30_DIFF_3_N LOC="V33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[8]) J4-30 |
|---|
| 289 | NET HDR2_32_DIFF_3_P LOC="V32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[8]) J4-32 |
|---|
| 290 | NET HDR2_34_SM_15_N LOC="V34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[7]) J4-34 |
|---|
| 291 | NET HDR2_36_SM_15_P LOC="W34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[7]) J4-36 |
|---|
| 292 | NET HDR2_38_SM_6_N LOC="AA33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[6]) J4-38 |
|---|
| 293 | NET HDR2_40_SM_6_P LOC="Y33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[6]) J4-40 |
|---|
| 294 | NET HDR2_42_SM_14_N LOC="AE34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[0]) J4-42 |
|---|
| 295 | NET HDR2_44_SM_14_P LOC="AF34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[0]) J4-44 |
|---|
| 296 | NET HDR2_46_SM_12_N LOC="AE33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[1]) J4-46 |
|---|
| 297 | NET HDR2_48_SM_12_P LOC="AF33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[1]) J4-48 |
|---|
| 298 | NET HDR2_50_SM_5_N LOC="AD34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[4]) J4-50 |
|---|
| 299 | NET HDR2_52_SM_5_P LOC="AC34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[4]) J4-52 |
|---|
| 300 | NET HDR2_54_SM_13_N LOC="AB32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[3]) J4-54 |
|---|
| 301 | NET HDR2_56_SM_13_P LOC="AC32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[3]) J4-56 |
|---|
| 302 | NET HDR2_58_SM_4_N LOC="AB33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXN[2]) J4-58 |
|---|
| 303 | NET HDR2_60_SM_4_P LOC="AC33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 (SYSMON External Input: VAUXP[2]) J4-60 |
|---|
| 304 | NET HDR2_62_SM_9_N LOC="AP32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 305 | NET HDR2_64_SM_9_P LOC="AN32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 306 | NET IIC_SCL_MAIN LOC="F9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 307 | NET IIC_SCL_SFP LOC="R26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 308 | NET IIC_SCL_VIDEO LOC="U27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 309 | NET IIC_SDA_MAIN LOC="F8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 310 | NET IIC_SDA_SFP LOC="U28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 311 | NET IIC_SDA_VIDEO LOC="T29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 312 | NET KEYBOARD_CLK LOC="T26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 313 | NET KEYBOARD_DATA LOC="T25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 314 | NET LCD_FPGA_DB4 LOC="T9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 315 | NET LCD_FPGA_DB5 LOC="G7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 316 | NET LCD_FPGA_DB6 LOC="G6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 317 | NET LCD_FPGA_DB7 LOC="T11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 318 | NET LCD_FPGA_E LOC="AC9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 319 | NET LCD_FPGA_RS LOC="J17"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 320 | NET LCD_FPGA_RW LOC="AC10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 321 | NET LOOPBK_114_N LOC="AG1"; # Bank 118, MGTRXN1_118, GTP_DUAL_X0Y1 |
|---|
| 322 | NET LOOPBK_114_N LOC="AH2"; # Bank 118, MGTTXN1_118, GTP_DUAL_X0Y1 |
|---|
| 323 | NET LOOPBK_114_P LOC="AH1"; # Bank 118, MGTRXP1_118, GTP_DUAL_X0Y1 |
|---|
| 324 | NET LOOPBK_114_P LOC="AJ2"; # Bank 118, MGTTXP1_118, GTP_DUAL_X0Y1 |
|---|
| 325 | NET LOOPBK_116_N LOC="R1"; # Bank 112, MGTRXN1_112, GTP_DUAL_X0Y3 |
|---|
| 326 | NET LOOPBK_116_N LOC="T2"; # Bank 112, MGTTXN1_112, GTP_DUAL_X0Y3 |
|---|
| 327 | NET LOOPBK_116_P LOC="T1"; # Bank 112, MGTRXP1_112, GTP_DUAL_X0Y3 |
|---|
| 328 | NET LOOPBK_116_P LOC="U2"; # Bank 112, MGTTXP1_112, GTP_DUAL_X0Y3 |
|---|
| 329 | NET MOUSE_CLK LOC="R27"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 330 | NET MOUSE_DATA LOC="U26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 331 | NET PC4_HALT_B LOC="W9"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 332 | NET PCIE_CLK_QO_N LOC="AF3"; # Bank 118, MGTREFCLKN_118, GTP_DUAL_X0Y1 |
|---|
| 333 | NET PCIE_CLK_QO_P LOC="AF4"; # Bank 118, MGTREFCLKP_118, GTP_DUAL_X0Y1 |
|---|
| 334 | NET PCIE_PRSNT_B_FPGA LOC="AF24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 335 | NET PCIE_RX_N LOC="AF1"; # Bank 118, MGTRXN0_118, GTP_DUAL_X0Y1 |
|---|
| 336 | NET PCIE_RX_P LOC="AE1"; # Bank 118, MGTRXP0_118, GTP_DUAL_X0Y1 |
|---|
| 337 | NET PCIE_TX_N LOC="AE2"; # Bank 118, MGTTXN0_118, GTP_DUAL_X0Y1 |
|---|
| 338 | NET PCIE_TX_P LOC="AD2"; # Bank 118, MGTTXP0_118, GTP_DUAL_X0Y1 |
|---|
| 339 | NET PHY_COL LOC="B32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 340 | NET PHY_CRS LOC="E34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 341 | NET PHY_INT LOC="H20"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 342 | NET PHY_MDC LOC="H19"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 343 | NET PHY_MDIO LOC="H13"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 344 | NET PHY_RESET LOC="J14"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 345 | NET PHY_RXCLK LOC="H17"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 346 | NET PHY_RXCTL_RXDV LOC="E32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 347 | NET PHY_RXD0 LOC="A33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 348 | NET PHY_RXD1 LOC="B33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 349 | NET PHY_RXD2 LOC="C33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 350 | NET PHY_RXD3 LOC="C32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 351 | NET PHY_RXD4 LOC="D32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 352 | NET PHY_RXD5 LOC="C34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 353 | NET PHY_RXD6 LOC="D34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 354 | NET PHY_RXD7 LOC="F33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 355 | NET PHY_RXER LOC="E33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 |
|---|
| 356 | NET PHY_TXC_GTXCLK LOC="J16"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 357 | NET PHY_TXCLK LOC="K17"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 358 | NET PHY_TXCTL_TXEN LOC="AJ10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 359 | NET PHY_TXD0 LOC="AF11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 360 | NET PHY_TXD1 LOC="AE11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 361 | NET PHY_TXD2 LOC="AH9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 362 | NET PHY_TXD3 LOC="AH10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 363 | NET PHY_TXD4 LOC="AG8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 364 | NET PHY_TXD5 LOC="AH8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 365 | NET PHY_TXD6 LOC="AG10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 366 | NET PHY_TXD7 LOC="AG11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 367 | NET PHY_TXER LOC="AJ9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 368 | NET PIEZO_SPEAKER LOC="G30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 369 | NET RESERVED1 LOC="AB23"; # Bank 0, Vcco=3.3V |
|---|
| 370 | NET RESERVED2 LOC="AC23"; # Bank 0, Vcco=3.3V |
|---|
| 371 | NET RREF LOC="V4"; # Bank 112, MGTRREF_112, GTP_DUAL_X0Y3 |
|---|
| 372 | NET SATA1_RX_N LOC="Y1"; # Bank 114, MGTRXN0_114, GTP_DUAL_X0Y2 |
|---|
| 373 | NET SATA1_RX_P LOC="W1"; # Bank 114, MGTRXP0_114, GTP_DUAL_X0Y2 |
|---|
| 374 | NET SATA1_TX_N LOC="W2"; # Bank 114, MGTTXN0_114, GTP_DUAL_X0Y2 |
|---|
| 375 | NET SATA1_TX_P LOC="V2"; # Bank 114, MGTTXP0_114, GTP_DUAL_X0Y2 |
|---|
| 376 | NET SATA2_RX_N LOC="AA1"; # Bank 114, MGTRXN1_114, GTP_DUAL_X0Y2 |
|---|
| 377 | NET SATA2_RX_P LOC="AB1"; # Bank 114, MGTRXP1_114, GTP_DUAL_X0Y2 |
|---|
| 378 | NET SATA2_TX_N LOC="AB2"; # Bank 114, MGTTXN1_114, GTP_DUAL_X0Y2 |
|---|
| 379 | NET SATA2_TX_P LOC="AC2"; # Bank 114, MGTTXP1_114, GTP_DUAL_X0Y2 |
|---|
| 380 | NET SATACLK_QO_N LOC="Y3"; # Bank 114, MGTREFCLKN_114, GTP_DUAL_X0Y2 |
|---|
| 381 | NET SATACLK_QO_P LOC="Y4"; # Bank 114, MGTREFCLKP_114, GTP_DUAL_X0Y2 |
|---|
| 382 | NET SFP_RX_N LOC="H1"; # Bank 116, MGTRXN0_116, GTP_DUAL_X0Y4 |
|---|
| 383 | NET SFP_RX_P LOC="G1"; # Bank 116, MGTRXP0_116, GTP_DUAL_X0Y4 |
|---|
| 384 | NET SFP_TX_DISABLE_FPGA LOC="K24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors |
|---|
| 385 | NET SFP_TX_N LOC="G2"; # Bank 116, MGTTXN0_116, GTP_DUAL_X0Y4 |
|---|
| 386 | NET SFP_TX_P LOC="F2"; # Bank 116, MGTTXP0_116, GTP_DUAL_X0Y4 |
|---|
| 387 | NET SGMII_RX_N LOC="P1"; # Bank 112, MGTRXN0_112, GTP_DUAL_X0Y3 |
|---|
| 388 | NET SGMII_RX_P LOC="N1"; # Bank 112, MGTRXP0_112, GTP_DUAL_X0Y3 |
|---|
| 389 | NET SGMII_TX_N LOC="N2"; # Bank 112, MGTTXN0_112, GTP_DUAL_X0Y3 |
|---|
| 390 | NET SGMII_TX_P LOC="M2"; # Bank 112, MGTTXP0_112, GTP_DUAL_X0Y3 |
|---|
| 391 | NET SGMIICLK_QO_N LOC="P3"; # Bank 112, MGTREFCLKN_112, GTP_DUAL_X0Y3 |
|---|
| 392 | NET SGMIICLK_QO_P LOC="P4"; # Bank 112, MGTREFCLKP_112, GTP_DUAL_X0Y3 |
|---|
| 393 | NET SMA_DIFF_CLK_IN_N LOC="H15"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 394 | NET SMA_DIFF_CLK_IN_P LOC="H14"; # Bank 3, Vcco=2.5V, No DCI |
|---|
| 395 | NET SMA_RX_N LOC="J1"; # Bank 116, MGTRXN1_116, GTP_DUAL_X0Y4 |
|---|
| 396 | NET SMA_RX_P LOC="K1"; # Bank 116, MGTRXP1_116, GTP_DUAL_X0Y4 |
|---|
| 397 | NET SMA_TX_N LOC="K2"; # Bank 116, MGTTXN1_116, GTP_DUAL_X0Y4 |
|---|
| 398 | NET SMA_TX_P LOC="L2"; # Bank 116, MGTTXP1_116, GTP_DUAL_X0Y4 |
|---|
| 399 | NET SPI_CE_B LOC="V9"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 400 | NET SRAM_ADV_LD_B LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 401 | NET SRAM_BW0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 402 | NET SRAM_BW1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 403 | NET SRAM_BW2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 404 | NET SRAM_BW3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 405 | NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 406 | NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 407 | NET SRAM_CS_B LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 408 | NET SRAM_D16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 409 | NET SRAM_D17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 410 | NET SRAM_D18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 411 | NET SRAM_D19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 412 | NET SRAM_D20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 413 | NET SRAM_D21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 414 | NET SRAM_D22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 415 | NET SRAM_D23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 416 | NET SRAM_D24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 417 | NET SRAM_D25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 418 | NET SRAM_D26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 419 | NET SRAM_D27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 420 | NET SRAM_D28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 421 | NET SRAM_D29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 422 | NET SRAM_D30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 423 | NET SRAM_D31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 424 | NET SRAM_DQP0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 425 | NET SRAM_DQP1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 426 | NET SRAM_DQP2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 427 | NET SRAM_DQP3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 428 | NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V |
|---|
| 429 | NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V |
|---|
| 430 | NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V |
|---|
| 431 | NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V |
|---|
| 432 | NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V |
|---|
| 433 | NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V |
|---|
| 434 | NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V |
|---|
| 435 | NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V |
|---|
| 436 | NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V |
|---|
| 437 | NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V |
|---|
| 438 | NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V |
|---|
| 439 | NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V |
|---|
| 440 | NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V |
|---|
| 441 | NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V |
|---|
| 442 | NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V |
|---|
| 443 | NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V |
|---|
| 444 | NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V |
|---|
| 445 | NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V |
|---|
| 446 | NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V |
|---|
| 447 | NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V |
|---|
| 448 | NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V |
|---|
| 449 | NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V |
|---|
| 450 | NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V |
|---|
| 451 | NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V |
|---|
| 452 | NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V |
|---|
| 453 | NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V |
|---|
| 454 | NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V |
|---|
| 455 | NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V |
|---|
| 456 | NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V |
|---|
| 457 | NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V |
|---|
| 458 | NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 459 | NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 460 | NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 461 | NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 462 | NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 463 | NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 464 | NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 465 | NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 466 | NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V |
|---|
| 467 | NET SRAM_MODE LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 468 | NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 469 | NET SYSACE_MPA00 LOC="G5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 470 | NET SYSACE_MPA01_USB_A0 LOC="N7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 471 | NET SYSACE_MPA02_USB_A1 LOC="N5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 472 | NET SYSACE_MPA03 LOC="P5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 473 | NET SYSACE_MPA04 LOC="R6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 474 | NET SYSACE_MPA05 LOC="M6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 475 | NET SYSACE_MPA06 LOC="L6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 476 | NET SYSACE_MPBRDY LOC="H5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 477 | NET SYSACE_MPCE LOC="M5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 478 | NET SYSACE_MPIRQ LOC="M7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 479 | NET SYSACE_MPOE_USB_RD_B LOC="N8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 480 | NET SYSACE_MPWE_USB_WR_B LOC="R9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 481 | NET SYSACE_USB_D0 LOC="P9"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 482 | NET SYSACE_USB_D1 LOC="T8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 483 | NET SYSACE_USB_D2 LOC="J7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 484 | NET SYSACE_USB_D3 LOC="H7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 485 | NET SYSACE_USB_D4 LOC="R7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 486 | NET SYSACE_USB_D5 LOC="U7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 487 | NET SYSACE_USB_D6 LOC="P7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 488 | NET SYSACE_USB_D7 LOC="P6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 489 | NET SYSACE_USB_D8 LOC="R8"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 490 | NET SYSACE_USB_D9 LOC="L5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 491 | NET SYSACE_USB_D10 LOC="L4"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 492 | NET SYSACE_USB_D11 LOC="K6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 493 | NET SYSACE_USB_D12 LOC="J5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 494 | NET SYSACE_USB_D13 LOC="T6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 495 | NET SYSACE_USB_D14 LOC="K7"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 496 | NET SYSACE_USB_D15 LOC="J6"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 497 | NET TRC_CLK LOC="AD9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 498 | NET TRC_TS1E LOC="AK9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 499 | NET TRC_TS1O LOC="AF10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 500 | NET TRC_TS2E LOC="AK8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 501 | NET TRC_TS2O LOC="AF9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 502 | NET TRC_TS3 LOC="AJ11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 503 | NET TRC_TS4 LOC="AK11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 504 | NET TRC_TS5 LOC="AD11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 505 | NET TRC_TS6 LOC="AD10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 506 | NET USB_CS_B LOC="P10"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 507 | NET USB_INT LOC="F5"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 508 | NET USB_RESET_B LOC="R11"; # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors |
|---|
| 509 | NET USER_CLK LOC="AH15"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 510 | NET VGA_IN_BLUE0 LOC="AC4"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 511 | NET VGA_IN_BLUE1 LOC="AC5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 512 | NET VGA_IN_BLUE2 LOC="AB6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 513 | NET VGA_IN_BLUE3 LOC="AB7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 514 | NET VGA_IN_BLUE4 LOC="AA5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 515 | NET VGA_IN_BLUE5 LOC="AB5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 516 | NET VGA_IN_BLUE6 LOC="AC7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 517 | NET VGA_IN_BLUE7 LOC="AD7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 518 | NET VGA_IN_CLAMP LOC="AH7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 519 | NET VGA_IN_COAST LOC="AG7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 520 | NET VGA_IN_DATA_CLK LOC="AH18"; # Bank 4, Vcco=3.3V, No DCI |
|---|
| 521 | NET VGA_IN_GREEN0 LOC="Y8"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 522 | NET VGA_IN_GREEN1 LOC="Y9"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 523 | NET VGA_IN_GREEN2 LOC="AD4"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 524 | NET VGA_IN_GREEN3 LOC="AD5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 525 | NET VGA_IN_GREEN4 LOC="AA6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 526 | NET VGA_IN_GREEN5 LOC="Y7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 527 | NET VGA_IN_GREEN6 LOC="AD6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 528 | NET VGA_IN_GREEN7 LOC="AE6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 529 | NET VGA_IN_HSOUT LOC="AE7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 530 | NET VGA_IN_ODD_EVEN_B LOC="W6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 531 | NET VGA_IN_RED0 LOC="AG5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 532 | NET VGA_IN_RED1 LOC="AF5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 533 | NET VGA_IN_RED2 LOC="W7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 534 | NET VGA_IN_RED3 LOC="V7"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 535 | NET VGA_IN_RED4 LOC="AH5"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 536 | NET VGA_IN_RED5 LOC="AG6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 537 | NET VGA_IN_RED6 LOC="Y11"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 538 | NET VGA_IN_RED7 LOC="W11"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 539 | NET VGA_IN_SOGOUT LOC="AF6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
| 540 | NET VGA_IN_VSOUT LOC="Y6"; # Bank 18, Vcco=3.3V, No DCI |
|---|
