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os2wb_dual.v @ 14

Revision 14, 49.3 KB checked in by pntsvt00, 14 years ago (diff)
commit per simulazione di os2wb e Top

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[6]	1	`timescale 1ns / 1ps
	2	//////////////////////////////////////////////////////////////////////////////////
	3	// Company: (C) Athree, 2009
	4	// Engineer: Dmitry Rozhdestvenskiy
	5	// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
	6	//
	7	// Design Name: Bridge from SPARC Core to Wishbone Master
	8	// Module Name: os2wb
	9	// Project Name: SPARC SoC single-core
	10	//
	11	// LICENSE:
	12	// This is a Free Hardware Design; you can redistribute it and/or
	13	// modify it under the terms of the GNU General Public License
	14	// version 2 as published by the Free Software Foundation.
	15	// The above named program is distributed in the hope that it will
	16	// be useful, but WITHOUT ANY WARRANTY; without even the implied
	17	// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	18	// See the GNU General Public License for more details.
	19	//
	20	//////////////////////////////////////////////////////////////////////////////////
[14]	21
	22	`ifdef DUALCORES
	23
[6]	24	module os2wb_dual(
	25	input clk,
	26	input rstn,
	27
	28	// Core interface
	29	input [ 4:0] pcx_req,
	30	input pcx_atom,
	31	input [123:0] pcx_data,
	32	output reg [ 4:0] pcx_grant,
	33	output reg cpx_ready,
	34	output reg [144:0] cpx_packet,
	35
	36	// Core 2nd interface
	37	input [ 4:0] pcx1_req,
	38	input pcx1_atom,
	39	input [123:0] pcx1_data,
	40	output reg [ 4:0] pcx1_grant,
	41	output reg cpx1_ready,
	42	output reg [144:0] cpx1_packet,
	43
	44	// Wishbone master interface
	45	input [ 63:0] wb_data_i,
	46	input wb_ack,
	47	output reg wb_cycle,
	48	output reg wb_strobe,
	49	output reg wb_we,
	50	output reg [ 7:0] wb_sel,
	51	output reg [ 63:0] wb_addr,
	52	output reg [ 63:0] wb_data_o,
	53
	54	// FPU interface
	55	output reg [123:0] fp_pcx,
	56	output reg fp_req,
	57	input [144:0] fp_cpx,
	58	input fp_rdy,
	59
	60	// Ethernet interrupt, sensed on posedge, mapped to vector 'd29
	61	input eth_int
	62	);
	63
	64	reg [123:0] pcx_packet_d; // Latched incoming PCX packet
	65	reg [123:0] pcx_packet_2nd; // Second packet for atomic (CAS)
	66	reg [ 4:0] pcx_req_d; // Latched request
	67	reg pcx_atom_d; // Latched atomic flasg
	68	reg [ 4:0] state; // FSM state
	69	reg [144:0] cpx_packet_1; // First CPX packet
	70	reg [144:0] cpx_packet_2; // Second CPX packet (for atomics and cached IFILLs)
	71	reg cpx_two_packet; // CPX answer is two-packet (!=atomic, SWAP has atomic==0 and answer is two-packet)
	72
	73	wire [111:0] inval_vect0; // Invalidate, instr/data, way
	74	wire [111:0] inval_vect1; // IFill may cause two D lines invalidation at a time
	75
	76	wire [1:0] othercachehit;
	77	wire [1:0] othercpuhit;
	78	wire [1:0] wayval0;
	79	wire [1:0] wayval1;
	80
	81	`define TEST_DRAM_1 5'b00000
	82	`define TEST_DRAM_2 5'b00001
	83	`define TEST_DRAM_3 5'b00010
	84	`define TEST_DRAM_4 5'b00011
	85	`define INIT_DRAM_1 5'b00100
	86	`define INIT_DRAM_2 5'b00101
	87	`define WAKEUP 5'b00110
	88	`define PCX_IDLE 5'b00111
	89	`define GOT_PCX_REQ 5'b01000
	90	`define PCX_REQ_2ND 5'b01001
	91	`define PCX_REQ_STEP1 5'b01010
	92	`define PCX_REQ_STEP1_1 5'b01011
	93	`define PCX_REQ_STEP2 5'b01100
	94	`define PCX_REQ_STEP2_1 5'b01101
	95	`define PCX_REQ_STEP3 5'b01110
	96	`define PCX_REQ_STEP3_1 5'b01111
	97	`define PCX_REQ_STEP4 5'b10000
	98	`define PCX_REQ_STEP4_1 5'b10001
	99	`define PCX_BIS 5'b10010
	100	`define PCX_BIS_1 5'b10011
	101	`define PCX_BIS_2 5'b10100
	102	`define CPX_READY_1 5'b10101
	103	`define CPX_READY_2 5'b10110
	104	`define PCX_REQ_STEP1_2 5'b10111
	105	`define PCX_UNKNOWN 5'b11000
	106	`define PCX_FP_1 5'b11001
	107	`define PCX_FP_2 5'b11010
	108	`define FP_WAIT 5'b11011
	109	`define CPX_FP 5'b11100
	110	`define CPX_SEND_ETH_IRQ 5'b11101
	111	`define CPX_INT_VEC_DIS 5'b11110
	112	`define PCX_REQ_CAS_COMPARE 5'b11111
	113
	114	`define MEM_SIZE 64'h00000000_10000000
	115
	116	`define TEST_DRAM 1
	117	`define DEBUGGING 1
	118
	119	reg cache_init;
	120	wire [3:0] dcache0_hit;
	121	wire [3:0] dcache1_hit;
	122	wire [3:0] icache_hit;
	123	reg multi_hit;
	124	reg multi_hit1;
	125	reg eth_int_d;
	126	reg eth_int_send;
	127	reg eth_int_sent;
	128	reg [3:0] cnt;
	129
	130	// PCX channel FIFO
	131	wire [129:0] pcx_data_fifo;
	132	wire pcx_fifo_empty;
	133	reg [ 4:0] pcx_req_1;
	134	reg [ 4:0] pcx_req_2;
	135	reg pcx_atom_1;
	136	reg pcx_atom_2;
	137	reg pcx_data_123_d;
	138
	139	// PCX 2nf channel FIFO
	140	wire [129:0] pcx1_data_fifo;
	141	wire pcx1_fifo_empty;
	142	reg [ 4:0] pcx1_req_1;
	143	reg [ 4:0] pcx1_req_2;
	144	reg pcx1_atom_1;
	145	reg pcx1_atom_2;
	146	reg pcx1_data_123_d;
	147
	148	reg fifo_rd;
	149	reg fifo_rd1;
	150
	151	always @(posedge clk)
	152	begin
	153	pcx_req_1<=pcx_req;
	154	pcx_atom_1<=pcx_atom;
	155	pcx_atom_2<=pcx_atom_1;
	156	pcx_req_2<=pcx_atom_1 ? pcx_req_1:5'b0;
	157	pcx_grant<=(pcx_req_1 \| pcx_req_2);
	158	pcx_data_123_d<=pcx_data[123];
	159
	160	pcx1_req_1<=pcx1_req;
	161	pcx1_atom_1<=pcx1_atom;
	162	pcx1_atom_2<=pcx1_atom_1;
	163	pcx1_req_2<=pcx1_atom_1 ? pcx1_req_1:5'b0;
	164	pcx1_grant<=(pcx1_req_1 \| pcx1_req_2);
	165	pcx1_data_123_d<=pcx1_data[123];
	166	end
	167
	168	/*pcx_fifo pcx_fifo_inst(
	169	// FIFO should be first word fall-through
	170	// It has no full flag as the core will send only limited number of requests,
	171	// in original design we used it 32 words deep
	172	// Just make it deeper if you experience overflow -
	173	// you can't just send no grant on full because the core expects immediate
	174	// grant for at least two requests for each zone
	175	.aclr(!rstn),
	176	.clock(clk),
	177	.data({pcx_atom_1,pcx_req_1,pcx_data}),
	178	.rdreq(fifo_rd),
	179	.wrreq((pcx_req_1!=5'b00000 && pcx_data[123]) \|\| (pcx_atom_2 && pcx_data_123_d)),
	180	// Second atomic packet for FPU may be invalid, but should be sent to FPU
	181	// so if the first atomic packet is valid we latch both
	182	.empty(pcx_fifo_empty),
	183	.q(pcx_data_fifo)
	184	);
	185	*/
[14]	186
[6]	187	pcx_fifo pcx_fifo_inst(
	188	.clk(clk),
	189	.rst(!rstn),
	190	.din({pcx_atom_1,pcx_req_1,pcx_data}),
	191	.rd_en(fifo_rd),
	192	.wr_en((pcx_req_1!=5'b00000 && pcx_data[123]) \|\| (pcx_atom_2 && pcx_data_123_d)),
	193	.empty(pcx_fifo_empty),
	194	.dout(pcx_data_fifo)
	195	);
	196
	197
	198	pcx_fifo pcx_fifo_inst1(
	199	.clk(clk),
	200	.rst(!rstn),
	201	.din({pcx1_atom_1,pcx1_req_1,pcx1_data}),
	202	.rd_en(fifo_rd1),
	203	.wr_en((pcx1_req_1!=5'b00000 && pcx1_data[123]) \|\| (pcx1_atom_2 && pcx1_data_123_d)),
	204	.empty(pcx1_fifo_empty),
	205	.dout(pcx1_data_fifo)
	206	);
	207	// --------------------------
	208
	209	reg wb_ack_d;
	210
	211	always @(posedge clk or negedge rstn)
	212	begin
	213	if(!rstn)
	214	eth_int_send<=0;
	215	else
	216	begin
	217	wb_ack_d<=wb_ack;
	218	eth_int_d<=eth_int;
	219	if(eth_int && !eth_int_d)
	220	eth_int_send<=1;
	221	else
	222	if(eth_int_sent)
	223	eth_int_send<=0;
	224	end
	225	end
	226	wire [123:0] pcx_packet;
	227	reg cpu;
	228	assign pcx_packet=cpu ? pcx1_data_fifo[123:0]:pcx_data_fifo[123:0];
	229	reg cpu2;
	230
	231	always @(posedge clk or negedge rstn)
	232	if(rstn==0)
	233	begin
	234	if(`TEST_DRAM)
	235	state<=`TEST_DRAM_1;
	236	else
	237	state<=`INIT_DRAM_1; // DRAM initialization is mandatory!
	238	cpx_ready<=0;
	239	fifo_rd<=0;
	240	cpx_packet<=145'b0;
	241	wb_cycle<=0;
	242	wb_strobe<=0;
	243	wb_we<=0;
	244	wb_sel<=0;
	245	wb_addr<=64'b0;
	246	wb_data_o<=64'b0;
	247	pcx_packet_d<=124'b0;
	248	fp_pcx<=124'b0;
	249	fp_req<=0;
	250	end
	251	else
	252	case(state)
	253	`TEST_DRAM_1:
	254	begin
	255	wb_cycle<=1;
	256	wb_strobe<=1;
	257	wb_sel<=8'hFF;
	258	wb_we<=1;
	259	state<=`TEST_DRAM_2;
	260	end
	261	`TEST_DRAM_2:
	262	if(wb_ack)
	263	begin
	264	wb_strobe<=0;
	265	if(wb_addr<`MEM_SIZE-8)
	266	begin
	267	wb_addr[31:0]<=wb_addr[31:0]+8;
	268	wb_data_o<={wb_addr[31:0]+8,wb_addr[31:0]+8};
	269	state<=`TEST_DRAM_1;
	270	end
	271	else
	272	begin
	273	state<=`TEST_DRAM_3;
	274	wb_cycle<=0;
	275	wb_sel<=0;
	276	wb_we<=0;
	277	wb_data_o<=64'b0;
	278	wb_addr<=64'b0;
	279	end
	280	end
	281	`TEST_DRAM_3:
	282	begin
	283	wb_cycle<=1;
	284	wb_strobe<=1;
	285	wb_sel<=8'hFF;
	286	state<=`TEST_DRAM_4;
	287	end
	288	`TEST_DRAM_4:
	289	if(wb_ack)
	290	begin
	291	wb_strobe<=0;
	292	if(wb_addr<`MEM_SIZE-8)
	293	begin
	294	if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]})
	295	begin
	296	wb_addr[31:0]<=wb_addr[31:0]+8;
	297	state<=`TEST_DRAM_3;
	298	end
	299	end
	300	else
	301	begin
	302	state<=`INIT_DRAM_1;
	303	wb_cycle<=0;
	304	wb_sel<=0;
	305	wb_we<=0;
	306	wb_data_o<=64'b0;
	307	wb_addr<=64'b0;
	308	end
	309	end
	310	`INIT_DRAM_1:
	311	begin
	312	wb_cycle<=1;
	313	wb_strobe<=1;
	314	wb_sel<=8'hFF;
	315	wb_we<=1;
	316	cache_init<=1; // We also init cache directories here
	317	state<=`INIT_DRAM_2;
	318	end
	319	`INIT_DRAM_2:
	320	if(wb_ack)
	321	begin
	322	wb_strobe<=0;
	323	if(wb_addr<`MEM_SIZE-8)
	324	begin
	325	wb_addr[31:0]<=wb_addr[31:0]+8;
	326	pcx_packet_d[64+11:64+4]<=pcx_packet_d[64+11:64+4]+1; // Address for cachedir init
	327	state<=`INIT_DRAM_1;
	328	end
	329	else
	330	begin
	331	state<=`WAKEUP;
	332	wb_cycle<=0;
	333	wb_sel<=0;
	334	wb_we<=0;
	335	cache_init<=0;
	336	wb_addr<=64'b0;
	337	end
	338	end
	339	`WAKEUP:
	340	begin
	341	cpx_packet<=145'h1700000000000000000000000000000010001;
	342	cpx_ready<=1;
	343	state<=`PCX_IDLE;
	344	end
	345	`PCX_IDLE:
	346	begin
	347	cnt<=0;
	348	cpx_packet<=145'b0;
	349	cpx_ready<=0;
	350	cpx1_packet<=145'b0;
	351	cpx1_ready<=0;
	352	cpx_two_packet<=0;
	353	multi_hit<=0;
	354	multi_hit1<=0;
	355	if(eth_int_send)
	356	begin
	357	state<=`CPX_SEND_ETH_IRQ;
	358	eth_int_sent<=1;
	359	end
	360	else
	361	if(!pcx_fifo_empty)
	362	begin
	363	pcx_req_d<=pcx_data_fifo[128:124];
	364	pcx_atom_d<=pcx_data_fifo[129];
	365	fifo_rd<=1;
	366	state<=`GOT_PCX_REQ;
	367	cpu<=0;
	368	cpu2<=0;
	369	end
	370	else
	371	if(!pcx1_fifo_empty)
	372	begin
	373	pcx_req_d<=pcx1_data_fifo[128:124];
	374	pcx_atom_d<=pcx1_data_fifo[129];
	375	fifo_rd1<=1;
	376	state<=`GOT_PCX_REQ;
	377	cpu<=1;
	378	cpu2<=1;
	379	end
	380	end
	381	`GOT_PCX_REQ:
	382	begin
	383	pcx_packet_d<=pcx_packet;
	384	if(`DEBUGGING)
	385	begin
	386	wb_sel[1:0]<=pcx_packet[113:112];
	387	wb_sel[2]<=1;
	388	end
	389	if(pcx_packet[103:64]==40'h9800000800 && pcx_packet[122:118]==5'b00001)
	390	begin
	391	state<=`CPX_INT_VEC_DIS;
	392	fifo_rd<=0;
	393	fifo_rd1<=0;
	394	end
	395	else
	396	if(pcx_atom_d==0)
	397	begin
	398	fifo_rd<=0;
	399	fifo_rd1<=0;
	400	if(pcx_packet[122:118]==5'b01010) // FP req
	401	begin
	402	state<=`PCX_FP_1;
	403	pcx_packet_2nd[123]<=0;
	404	end
	405	else
	406	state<=`PCX_REQ_STEP1;
	407	end
	408	else
	409	state<=`PCX_REQ_2ND;
	410	end
	411	`PCX_REQ_2ND:
	412	begin
	413	pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics
	414	if(`DEBUGGING)
	415	if(pcx_fifo_empty)
	416	wb_sel<=8'h67;
	417	fifo_rd<=0;
	418	fifo_rd1<=0;
	419	if(pcx_packet_d[122:118]==5'b01010) // FP req
	420	state<=`PCX_FP_1;
	421	else
	422	state<=`PCX_REQ_STEP1;
	423	end
	424	`PCX_REQ_STEP1:
	425	begin
	426	if(pcx_packet_d[111]==1'b1) // Invalidate request
	427	begin
	428	cpx_packet_1[144]<=1; // Valid
	429	cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK
	430	cpx_packet_1[139]<=1; // L2 miss
	431	cpx_packet_1[138:137]<=0; // Error
	432	cpx_packet_1[136]<=pcx_packet_d[117]; // Non-cacheble
	433	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	434	cpx_packet_1[133:131]<=0; // Way valid
	435	cpx_packet_1[130]<=((pcx_packet_d[122:118]==5'b10000) && (pcx_req_d==5'b10000)) ? 1:0; // Four byte fill
	436	cpx_packet_1[129]<=pcx_atom_d;
	437	cpx_packet_1[128]<=pcx_packet_d[110]; // Prefetch
	438	cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/BIS/,pcx_packet_d[122:118]==5'b00000 ? 2'b01:2'b10,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],112'b0};
	439	state<=`CPX_READY_1;
	440	end
	441	else
	442	if(pcx_packet_d[122:118]!=5'b01001) // Not INT
	443	begin
	444	wb_cycle<=1'b1;
	445	wb_strobe<=1'b1;
	446	if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) \|\| pcx_packet_d[122:118]==5'b00010 \|\| pcx_packet_d[122:118]==5'b00100 \|\| pcx_packet_d[122:118]==5'b00110)
	447	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first
	448	else
	449	if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4])
	450	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill
	451	else
	452	if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8
	453	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000};
	454	else
	455	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3],3'b000};
	456	wb_data_o<=pcx_packet_d[63:0];
	457	state<=`PCX_REQ_STEP1_1;
	458	end
	459	else
	460	//if((pcx_packet_d[12:10]!=3'b000) && !pcx_packet_d[117]) // Not FLUSH int and not this core
	461	// state<=`PCX_IDLE;
	462	//else
	463	state<=`CPX_READY_1;
	464	case(pcx_packet_d[122:118]) // Packet type
	465	5'b00000://Load
	466	begin
	467	wb_we<=0;
	468	if(!pcx_req_d[4])
	469	wb_sel<=8'b11111111; // DRAM requests are always 128 bit
	470	else
	471	case(pcx_packet_d[106:104]) //Size
	472	3'b000://Byte
	473	case(pcx_packet_d[64+2:64])
	474	3'b000:wb_sel<=8'b10000000;
	475	3'b001:wb_sel<=8'b01000000;
	476	3'b010:wb_sel<=8'b00100000;
	477	3'b011:wb_sel<=8'b00010000;
	478	3'b100:wb_sel<=8'b00001000;
	479	3'b101:wb_sel<=8'b00000100;
	480	3'b110:wb_sel<=8'b00000010;
	481	3'b111:wb_sel<=8'b00000001;
	482	endcase
	483	3'b001://Halfword
	484	case(pcx_packet_d[64+2:64+1])
	485	2'b00:wb_sel<=8'b11000000;
	486	2'b01:wb_sel<=8'b00110000;
	487	2'b10:wb_sel<=8'b00001100;
	488	2'b11:wb_sel<=8'b00000011;
	489	endcase
	490	3'b010://Word
	491	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	492	3'b011://Doubleword
	493	wb_sel<=8'b11111111;
	494	3'b100://Quadword
	495	wb_sel<=8'b11111111;
	496	3'b111://Cacheline
	497	wb_sel<=8'b11111111;
	498	default:
	499	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	500	endcase
	501	end
	502	5'b00001://Store
	503	begin
	504	wb_we<=1;
	505	if(pcx_packet_d[110:109]!=2'b00) //Block (or init) store
	506	wb_sel<=8'b11111111; // Blocks are always 64 bit
	507	else
	508	case(pcx_packet_d[106:104]) //Size
	509	3'b000://Byte
	510	case(pcx_packet_d[64+2:64])
	511	3'b000:wb_sel<=8'b10000000;
	512	3'b001:wb_sel<=8'b01000000;
	513	3'b010:wb_sel<=8'b00100000;
	514	3'b011:wb_sel<=8'b00010000;
	515	3'b100:wb_sel<=8'b00001000;
	516	3'b101:wb_sel<=8'b00000100;
	517	3'b110:wb_sel<=8'b00000010;
	518	3'b111:wb_sel<=8'b00000001;
	519	endcase
	520	3'b001://Halfword
	521	case(pcx_packet_d[64+2:64+1])
	522	2'b00:wb_sel<=8'b11000000;
	523	2'b01:wb_sel<=8'b00110000;
	524	2'b10:wb_sel<=8'b00001100;
	525	2'b11:wb_sel<=8'b00000011;
	526	endcase
	527	3'b010://Word
	528	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	529	3'b011://Doubleword
	530	wb_sel<=8'b11111111;
	531	default:
	532	if(`DEBUGGING)
	533	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	534	endcase
	535	end
	536	5'b00010://CAS
	537	begin
	538	wb_we<=0; //Load first
	539	wb_sel<=8'b11111111; // CAS loads are as cacheline
	540	end
	541	5'b00100://STRLOAD
	542	begin
	543	wb_we<=0;
	544	wb_sel<=8'b11111111; // Stream loads are always 128 bit
	545	end
	546	5'b00101://STRSTORE
	547	begin
	548	wb_we<=1;
	549	case(pcx_packet_d[106:104]) //Size
	550	3'b000://Byte
	551	case(pcx_packet_d[64+2:64])
	552	3'b000:wb_sel<=8'b10000000;
	553	3'b001:wb_sel<=8'b01000000;
	554	3'b010:wb_sel<=8'b00100000;
	555	3'b011:wb_sel<=8'b00010000;
	556	3'b100:wb_sel<=8'b00001000;
	557	3'b101:wb_sel<=8'b00000100;
	558	3'b110:wb_sel<=8'b00000010;
	559	3'b111:wb_sel<=8'b00000001;
	560	endcase
	561	3'b001://Halfword
	562	case(pcx_packet_d[64+2:64+1])
	563	2'b00:wb_sel<=8'b11000000;
	564	2'b01:wb_sel<=8'b00110000;
	565	2'b10:wb_sel<=8'b00001100;
	566	2'b11:wb_sel<=8'b00000011;
	567	endcase
	568	3'b010://Word
	569	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	570	3'b011://Doubleword
	571	wb_sel<=8'b11111111;
	572	3'b100://Quadword
	573	wb_sel<=8'b11111111;
	574	3'b111://Cacheline
	575	wb_sel<=8'b11111111;
	576	default:
	577	wb_sel<=8'b01011010; // Unreal eye-catching value for debug
	578	endcase
	579	end
	580	5'b00110://SWAP/LDSTUB
	581	begin
	582	wb_we<=0; // Load first, as CAS
	583	wb_sel<=8'b11111111; // SWAP/LDSTUB loads are as cacheline
	584	end
	585	5'b01001://INT
	586	if(pcx_packet_d[117]) // Flush
	587	begin
	588	cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
	589	//cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
	590	//cpx_two_packet<=1;
	591	//cpu2<=!cpu; // Flush should be sent to both cores
	592	end
	593	else // Tread-to-thread interrupt
	594	begin
	595	cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
	596	cpu<=pcx_packet_d[10];
	597	end
	598	//5'b01010: FP1 - processed by separate state
	599	//5'b01011: FP2 - processed by separate state
	600	//5'b01101: FWDREQ - not implemented
	601	//5'b01110: FWDREPL - not implemented
	602	5'b10000://IFILL
	603	begin
	604	wb_we<=0;
	605	if(pcx_req_d[4]) // I/O access
	606	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	607	else
	608	wb_sel<=8'b11111111;
	609	end
	610	default:
	611	begin
	612	wb_we<=0;
	613	wb_sel<=8'b10101010; // Unreal eye-catching value for debug
	614	end
	615	endcase
	616	end
	617	`PCX_REQ_STEP1_1:
	618	state<=`PCX_REQ_STEP1_2; // Delay for L1 directory
	619	`PCX_REQ_STEP1_2:
	620	begin
	621	if(wb_ack \|\| wb_ack_d)
	622	begin
	623	cpx_packet_1[144]<=1; // Valid
	624	cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) \|\| (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill
	625	cpx_packet_1[138:137]<=0; // Error
	626	cpx_packet_1[136]<=pcx_packet_d[117] \|\| (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too
	627	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	628	if((pcx_packet_d[122:118]==5'b00000 && !pcx_packet_d[117] && !pcx_packet_d[110]) \|\| (pcx_packet_d[122:118]==5'b10000)) // Cacheble Load or IFill
	629	cpx_packet_1[133:131]<={othercachehit[0],wayval0};
	630	else
	631	cpx_packet_1[133:131]<=3'b000; // Way valid
	632	if(pcx_packet_d[122:118]==5'b00100) // Strload
	633	cpx_packet_1[130]<=pcx_packet_d[106]; // A
	634	else
	635	if(pcx_packet_d[122:118]==5'b00101) // Stream store
	636	cpx_packet_1[130]<=pcx_packet_d[108]; // A
	637	else
	638	cpx_packet_1[130]<=((pcx_packet_d[122:118]==5'b10000) && pcx_req_d[4]) ? 1:0; // Four byte fill
	639	if(pcx_packet_d[122:118]==5'b00100) // Strload
	640	cpx_packet_1[129]<=pcx_packet_d[105]; // B
	641	else
	642	cpx_packet_1[129]<=pcx_atom_d \|\| (pcx_packet_d[122:118]==5'b00110); // SWAP is single-packet but needs atom in CPX
	643	cpx_packet_1[128]<=pcx_packet_d[110] && pcx_packet_d[122:118]==5'b00000; // Prefetch
	644	cpx_packet_2[144]<=1; // Valid
	645	cpx_packet_2[139]<=0; // L2 miss
	646	cpx_packet_2[138:137]<=0; // Error
	647	cpx_packet_2[136]<=pcx_packet_d[117] \|\| (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too
	648	cpx_packet_2[135:134]<=pcx_packet_d[113:112]; // Thread ID
	649	if(pcx_packet_d[122:118]==5'b10000) // IFill
	650	cpx_packet_2[133:131]<={othercachehit[1],wayval1};
	651	else
	652	cpx_packet_2[133:131]<=3'b000; // Way valid
	653	cpx_packet_2[130]<=0; // Four byte fill
	654	cpx_packet_2[129]<=pcx_atom_d \|\| (pcx_packet_d[122:118]==5'b00110) \|\| ((pcx_packet_d[122:118]==5'b10000) && !pcx_req_d[4]);
	655	cpx_packet_2[128]<=0; // Prefetch
	656	wb_strobe<=0;
	657	wb_sel<=8'b0;
	658	wb_addr<=64'b0;
	659	wb_data_o<=64'b0;
	660	wb_we<=0;
	661	case(pcx_packet_d[122:118]) // Packet type
	662	5'b00000://Load
	663	begin
	664	cpx_packet_1[143:140]<=4'b0000; // Type
	665	if(!pcx_req_d[4])
	666	begin
	667	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	668	state<=`PCX_REQ_STEP2;
	669	end
	670	else
	671	case(pcx_packet_d[106:104]) //Size
	672	3'b000://Byte
	673	begin
	674	case(pcx_packet_d[64+2:64])
	675	3'b000:cpx_packet_1[127:0]<={wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56],wb_data_i[63:56]};
	676	3'b001:cpx_packet_1[127:0]<={wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48],wb_data_i[55:48]};
	677	3'b010:cpx_packet_1[127:0]<={wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40],wb_data_i[47:40]};
	678	3'b011:cpx_packet_1[127:0]<={wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32],wb_data_i[39:32]};
	679	3'b100:cpx_packet_1[127:0]<={wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24],wb_data_i[31:24]};
	680	3'b101:cpx_packet_1[127:0]<={wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16],wb_data_i[23:16]};
	681	3'b110:cpx_packet_1[127:0]<={wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8],wb_data_i[15: 8]};
	682	3'b111:cpx_packet_1[127:0]<={wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0],wb_data_i[ 7: 0]};
	683	endcase
	684	wb_cycle<=0;
	685	state<=`CPX_READY_1;
	686	end
	687	3'b001://Halfword
	688	begin
	689	case(pcx_packet_d[64+2:64+1])
	690	2'b00:cpx_packet_1[127:0]<={wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48],wb_data_i[63:48]};
	691	2'b01:cpx_packet_1[127:0]<={wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32],wb_data_i[47:32]};
	692	2'b10:cpx_packet_1[127:0]<={wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16],wb_data_i[31:16]};
	693	2'b11:cpx_packet_1[127:0]<={wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0],wb_data_i[15: 0]};
	694	endcase
	695	wb_cycle<=0;
	696	state<=`CPX_READY_1;
	697	end
	698	3'b010://Word
	699	begin
	700	if(pcx_packet_d[64+2]==0)
	701	cpx_packet_1[127:0]<={wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32]};
	702	else
	703	cpx_packet_1[127:0]<={wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0]};
	704	wb_cycle<=0;
	705	state<=`CPX_READY_1;
	706	end
	707	3'b011://Doubleword
	708	begin
	709	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	710	wb_cycle<=0;
	711	state<=`CPX_READY_1;
	712	end
	713	3'b100://Quadword
	714	begin
	715	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	716	wb_cycle<=0;
	717	state<=`CPX_READY_1; // 16 byte access to PROM should just duplicate the data
	718	end
	719	3'b111://Cacheline
	720	begin
	721	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	722	wb_cycle<=0;
	723	state<=`CPX_READY_1; // 16 byte access to PROM should just duplicate the data
	724	end
	725	default:
	726	begin
	727	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	728	wb_cycle<=0;
	729	state<=`PCX_UNKNOWN;
	730	end
	731	endcase
	732	end
	733	5'b00001://Store
	734	begin
	735	cpx_packet_1[143:140]<=4'b0100; // Type
	736	cpx_packet_1[127:0]<={2'b0,pcx_packet_d[109]/BIS/,2'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	737	// if((pcx_packet_d[110:109]==2'b01) && (pcx_packet_d[64+5:64]==0) && !inval_vect0[3] && !inval_vect1[3]) // Block init store
	738	// state<=`PCX_BIS;
	739	// else
	740	// begin
	741	wb_cycle<=0;
	742	state<=`CPX_READY_1;
	743	// end
	744	end
	745	5'b00010://CAS
	746	begin
	747	cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
	748	cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
	749	cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	750	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	751	state<=`PCX_REQ_STEP2;
	752	end
	753	5'b00100://STRLOAD
	754	begin
	755	cpx_packet_1[143:140]<=4'b0010; // Type
	756	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	757	state<=`PCX_REQ_STEP2;
	758	end
	759	5'b00101://STRSTORE
	760	begin
	761	cpx_packet_1[143:140]<=4'b0110; // Type
	762	cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	763	wb_cycle<=0;
	764	state<=`CPX_READY_1;
	765	end
	766	5'b00110://SWAP/LDSTUB
	767	begin
	768	cpx_packet_1[143:140]<=4'b0000; // Load return for first packet
	769	cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet
	770	cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0};
	771	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	772	state<=`PCX_REQ_STEP2;
	773	end
	774	5'b10000://IFILL
	775	begin
	776	cpx_packet_1[143:140]<=4'b0001; // Type
	777	cpx_packet_2[143:140]<=4'b0001; // Type
	778	if(pcx_req_d[4]) // I/O access
	779	begin
	780	if(pcx_packet_d[64+2]==0)
	781	cpx_packet_1[127:0]<={wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32],wb_data_i[63:32]};
	782	else
	783	cpx_packet_1[127:0]<={wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0],wb_data_i[31:0]};
	784	state<=`CPX_READY_1;
	785	wb_cycle<=0;
	786	end
	787	else
	788	begin
	789	cpx_packet_1[127:0]<={wb_data_i,wb_data_i};
	790	state<=`PCX_REQ_STEP2;
	791	end
	792	end
	793	default:
	794	begin
	795	wb_cycle<=0;
	796	state<=`PCX_UNKNOWN;
	797	end
	798	endcase
	799	end
	800	end
	801	`PCX_REQ_STEP2: // IFill, Load/strload, CAS, SWAP, LDSTUB - alwas load
	802	begin
	803	wb_strobe<=1'b1;
	804	if(pcx_packet_d[122:118]==5'b10000)
	805	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b01000};
	806	else
	807	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b1000};
	808	wb_sel<=8'b11111111; // It is always full width for subsequent IFill and load accesses
	809	state<=`PCX_REQ_STEP2_1;
	810	end
	811	`PCX_REQ_STEP2_1:
	812	if(wb_ack==1)
	813	begin
	814	wb_strobe<=0;
	815	wb_sel<=8'b0;
	816	wb_addr<=64'b0;
	817	wb_data_o<=64'b0;
	818	wb_we<=0;
	819	cpx_packet_1[63:0]<=wb_data_i;
	820	if((pcx_packet_d[122:118]!=5'b00000) && (pcx_packet_d[122:118]!=5'b00100))
	821	if(pcx_packet_d[122:118]!=5'b00010) // IFill, SWAP
	822	state<=`PCX_REQ_STEP3;
	823	else
	824	state<=`PCX_REQ_CAS_COMPARE; // CAS
	825	else
	826	begin
	827	wb_cycle<=0;
	828	state<=`CPX_READY_1;
	829	end
	830	end
	831	`PCX_REQ_CAS_COMPARE:
	832	begin
	833	cpx_two_packet<=1;
	834	if(pcx_packet_d[106:104]==3'b010) // 32-bit
	835	case(pcx_packet_d[64+3:64+2])
	836	2'b00:state<=cpx_packet_1[127:96]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	837	2'b01:state<=cpx_packet_1[95:64]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	838	2'b10:state<=cpx_packet_1[63:32]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	839	2'b11:state<=cpx_packet_1[31:0]==pcx_packet_d[63:32] ? `PCX_REQ_STEP3:`CPX_READY_1;
	840	endcase
	841	else
	842	if(pcx_packet_d[64+3]==0)
	843	state<=cpx_packet_1[127:64]==pcx_packet_d[63:0] ? `PCX_REQ_STEP3:`CPX_READY_1;
	844	else
	845	state<=cpx_packet_1[63:0]==pcx_packet_d[63:0] ? `PCX_REQ_STEP3:`CPX_READY_1;
	846	end
	847	`PCX_REQ_STEP3: // 256-bit IFILL; CAS, SWAP and LDSTUB store
	848	begin
	849	if(pcx_packet_d[122:118]==5'b10000)
	850	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b10000};
	851	else
	852	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3],3'b000}; // CAS or SWAP save
	853	cpx_two_packet<=1;
	854	if(pcx_packet_d[122:118]==5'b10000)
	855	wb_we<=0;
	856	else
	857	wb_we<=1;
	858	wb_strobe<=1'b1;
	859	if(pcx_packet_d[122:118]==5'b00010) // CAS
	860	if(pcx_packet_d[106:104]==3'b010)
	861	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111;
	862	else
	863	wb_sel<=8'b11111111; //CASX
	864	else
	865	if(pcx_packet_d[122:118]==5'b00110) //SWAP or LDSTUB
	866	if(pcx_packet_d[106:104]==3'b000) //LDSTUB
	867	case(pcx_packet_d[64+2:64])
	868	3'b000:wb_sel<=8'b10000000;
	869	3'b001:wb_sel<=8'b01000000;
	870	3'b010:wb_sel<=8'b00100000;
	871	3'b011:wb_sel<=8'b00010000;
	872	3'b100:wb_sel<=8'b00001000;
	873	3'b101:wb_sel<=8'b00000100;
	874	3'b110:wb_sel<=8'b00000010;
	875	3'b111:wb_sel<=8'b00000001;
	876	endcase
	877	else
	878	wb_sel<=(pcx_packet_d[64+2]==0) ? 8'b11110000:8'b00001111; ///SWAP is always 32-bit
	879	else
	880	wb_sel<=8'b11111111; // It is always full width for subsequent IFill accesses
	881	if(pcx_packet_d[122:118]==5'b00110) //SWAP or LDSTUB
	882	wb_data_o<={pcx_packet_d[63:32],pcx_packet_d[63:32]};
	883	// wb_data_o<=pcx_packet_d[63:0];
	884	else
	885	wb_data_o<=pcx_packet_2nd[63:0]; // CAS store second packet data
	886	// if(pcx_packet_d[106:104]==3'b010)
	887	// wb_data_o<={pcx_packet_2nd[63:32],pcx_packet_2nd[63:32]}; // CAS store second packet data
	888	// else
	889	// wb_data_o<=pcx_packet_2nd[63:0];
	890	state<=`PCX_REQ_STEP3_1;
	891	end
	892	`PCX_REQ_STEP3_1:
	893	if(wb_ack==1)
	894	begin
	895	wb_strobe<=0;
	896	wb_sel<=8'b0;
	897	wb_addr<=64'b0;
	898	wb_we<=0;
	899	wb_data_o<=64'b0;
	900	if(pcx_packet_d[122:118]==5'b10000) // IFill
	901	begin
	902	cpx_packet_2[127:64]<=wb_data_i;
	903	state<=`PCX_REQ_STEP4;
	904	end
	905	else
	906	begin
	907	wb_cycle<=0;
	908	state<=`CPX_READY_1;
	909	end
	910	end
	911	`PCX_REQ_STEP4: // 256-bit IFILL only
	912	begin
	913	wb_strobe<=1'b1;
	914	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b11000};
	915	wb_sel<=8'b11111111; // It is always full width for subsequent accesses
	916	state<=`PCX_REQ_STEP4_1;
	917	end
	918	`PCX_REQ_STEP4_1:
	919	if(wb_ack==1)
	920	begin
	921	wb_cycle<=0;
	922	wb_strobe<=0;
	923	wb_sel<=8'b0;
	924	wb_addr<=64'b0;
	925	wb_we<=0;
	926	cpx_packet_2[63:0]<=wb_data_i;
	927	state<=`CPX_READY_1;
	928	end
	929	`PCX_BIS: // Block init store
	930	begin
	931	wb_strobe<=1'b1;
	932	wb_we<=1;
	933	wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+6],6'b001000};
	934	wb_sel<=8'b11111111;
	935	wb_data_o<=64'b0;
	936	state<=`PCX_BIS_1;
	937	end
	938	`PCX_BIS_1:
	939	if(wb_ack)
	940	begin
	941	wb_strobe<=0;
	942	if(wb_addr[39:0]<(pcx_packet_d[64+39:64]+8*7))
	943	state<=`PCX_BIS_2;
	944	else
	945	begin
	946	wb_cycle<=0;
	947	wb_sel<=0;
	948	wb_we<=0;
	949	wb_addr<=64'b0;
	950	state<=`CPX_READY_1;
	951	end
	952	end
	953	`PCX_BIS_2:
	954	begin
	955	wb_strobe<=1'b1;
	956	wb_addr[5:0]<=wb_addr[5:0]+8;
	957	state<=`PCX_BIS_1;
	958	end
	959	`PCX_FP_1:
	960	begin
	961	fp_pcx<=pcx_packet_d;
	962	fp_req<=1;
	963	state<=`PCX_FP_2;
	964	if(`DEBUGGING)
	965	begin
	966	wb_addr<=pcx_packet_d[103:64];
	967	wb_data_o<=pcx_packet_d[63:0];
	968	wb_sel<=8'h22;
	969	end
	970	end
	971	`PCX_FP_2:
	972	begin
	973	fp_pcx<=pcx_packet_2nd;
	974	state<=`FP_WAIT;
	975	if(`DEBUGGING)
	976	begin
	977	wb_addr<=pcx_packet_2nd[103:64];
	978	wb_data_o<=pcx_packet_d[63:0];
	979	wb_sel<=8'h23;
	980	end
	981	end
	982	`FP_WAIT:
	983	begin
	984	fp_pcx<=124'b0;
	985	fp_req<=0;
	986	if(fp_rdy)
	987	state<=`CPX_FP;
	988	if(`DEBUGGING)
	989	wb_sel<=8'h24;
	990	end
	991	`CPX_FP:
	992	if(fp_cpx[144]) // Packet valid
	993	begin
	994	cpx_packet_1<=fp_cpx;
	995	state<=`CPX_READY_1;
	996	if(`DEBUGGING)
	997	begin
	998	wb_addr<=fp_cpx[63:0];
	999	wb_data_o<=fp_cpx[127:64];
	1000	end
	1001	end
	1002	else
	1003	if(!fp_rdy)
	1004	state<=`FP_WAIT; // Else wait for another one if it is not here still
	1005	`CPX_SEND_ETH_IRQ:
	1006	begin
	1007	cpx_packet_1<=145'h1_7_000_000000000000001D_000000000000_001D;
	1008	eth_int_sent<=0;
	1009	state<=`CPX_READY_1;
	1010	end
	1011	`CPX_INT_VEC_DIS:
	1012	begin
	1013	//if(pcx_packet_d[12:10]==3'b000) // Send interrupt only if it is for this core
	1014	cpx_two_packet<=1;
	1015	cpu2<=pcx_packet_d[10];
	1016	cpx_packet_1[144:140]<=5'b10100;
	1017	cpx_packet_1[139:137]<=0;
	1018	cpx_packet_1[136]<=1;
	1019	cpx_packet_1[135:134]<=pcx_packet_d[113:112]; // Thread ID
	1020	cpx_packet_1[133:130]<=0;
	1021	cpx_packet_1[129]<=pcx_atom_d;
	1022	cpx_packet_1[128]<=0;
	1023	cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],112'b0};
	1024	cpx_packet_2<={9'h170,54'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]};
	1025	state<=`CPX_READY_1;
	1026	end
	1027	`CPX_READY_1:
	1028	begin
	1029	if(!cpu)
	1030	begin
	1031	cpx_ready<=1;
	1032	cpx_packet<=cpx_packet_1;
	1033	if(othercpuhit[0])
	1034	begin
	1035	cpx1_ready<=1;
	1036	cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b001,pcx_packet_d[64+11:64+6],inval_vect0};
	1037	end
	1038	end
	1039	else
	1040	begin
	1041	cpx1_ready<=1;
	1042	cpx1_packet<=cpx_packet_1;
	1043	if(othercpuhit[0])
	1044	begin
	1045	cpx_ready<=1;
	1046	cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b000,pcx_packet_d[64+11:64+6],inval_vect0};
	1047	end
	1048	end
	1049	cnt<=cnt+1;
	1050	if(`DEBUGGING)
	1051	if(multi_hit \|\| multi_hit1)
	1052	wb_sel<=8'h11;
	1053	state<=`CPX_READY_2;
	1054	end
	1055	`CPX_READY_2:
	1056	begin
	1057	if(cpx_two_packet && !cpu2)
	1058	begin
	1059	cpx_ready<=1;
	1060	cpx_packet<=cpx_packet_2;
	1061	end
	1062	else
	1063	if(cpu2 && othercpuhit[1])
	1064	begin
	1065	cpx_ready<=1;
	1066	cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b000,pcx_packet_d[64+11:64+6],inval_vect1};
	1067	end
	1068	else
	1069	begin
	1070	cpx_ready<=0;
	1071	cpx_packet<=145'b0;
	1072	end
	1073	if(cpx_two_packet && cpu2)
	1074	begin
	1075	cpx1_ready<=1;
	1076	cpx1_packet<=cpx_packet_2;
	1077	end
	1078	else
	1079	if(!cpu2 && othercpuhit[1])
	1080	begin
	1081	cpx1_ready<=1;
	1082	cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b001,pcx_packet_d[64+11:64+6],inval_vect1};
	1083	end
	1084	else
	1085	begin
	1086	cpx1_ready<=0;
	1087	cpx1_packet<=145'b0;
	1088	end
	1089	state<=`PCX_IDLE;
	1090	end
	1091	`PCX_UNKNOWN:
	1092	begin
	1093	wb_sel<=8'b10100101; // Illegal eye-catching value for debugging
	1094	state<=`PCX_IDLE;
	1095	end
	1096	endcase
	1097
	1098	l1dir l1dir_inst(
	1099	.clk(clk),
	1100	.reset(!rstn),
	1101
	1102	.cpu(cpu), // Issuing CPU number
	1103	.strobe(state==`GOT_PCX_REQ),
	1104	.way(pcx_packet[108:107]), // Way to allocate for allocating loads
	1105	.address(pcx_packet[64+39:64]),
	1106	.load(pcx_packet[122:118]==5'b00000),
	1107	.ifill(pcx_packet[122:118]==5'b10000),
	1108	.store(pcx_packet[122:118]==5'b00001),
	1109	.cas(pcx_packet[122:118]==5'b00010),
	1110	.swap(pcx_packet[122:118]==5'b00110),
	1111	.strload(pcx_packet[122:118]==5'b00100),
	1112	.strstore(pcx_packet[122:118]==5'b00101),
	1113	.cacheable((!pcx_packet[117]) && (!pcx_req_d[4])),
	1114	.prefetch(pcx_packet[110]),
	1115	.invalidate(pcx_packet[111]),
	1116	.blockstore(pcx_packet[109] \| pcx_packet[110]),
	1117
	1118	.inval_vect0(inval_vect0), // Invalidation vector
	1119	.inval_vect1(inval_vect1),
	1120	.othercachehit(othercachehit), // Other cache hit in the same CPU, wayval0/wayval1
	1121	.othercpuhit(othercpuhit), // Any cache hit in the other CPU, wayval0/wayval1
	1122	.wayval0(wayval0), // Way valid
	1123	.wayval1(wayval1), // Second way valid for ifill
	1124	.ready(ready) // Directory init done
	1125	);
	1126
[14]	1127	endmodule
	1128
	1129	`endif

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source: XOpenSparcT1/trunk/os2wb/os2wb_dual.v @ 14

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