Changeset 14 in XOpenSparcT1

Timestamp:

03/24/11 14:47:26 (13 years ago)

Author:

pntsvt00

Message:

commit per simulazione di os2wb e Top

Location:

trunk

Files:

• Top/W1.v (modified) (1 diff)
• os2wb/os2wb.v (modified) (2 diffs)
• os2wb/os2wb_dual.v (modified) (3 diffs)
• sim/simula.do (modified) (2 diffs)

trunk/Top/W1.v

@@ -86 +86 @@
    output            flash_cen,
    output            flash_clk,
-   output            flash_adv,
+   output            flash_adv, //FIXME it seems useless 
    output            flash_rst
 );

trunk/os2wb/os2wb.v

@@ -172 +172 @@
 );
 */
+reg fifo_rd;
+wire [123:0] pcx_packet;
+
+
 pcx_fifo pcx_fifo_inst( 
     .clk(clk),
@@ -199 +203 @@
       end
 
-reg fifo_rd;
-wire [123:0] pcx_packet;
+
 assign pcx_packet=pcx_data_fifo[123:0];
 

trunk/os2wb/os2wb_dual.v

@@ -19 +19 @@
 //
 //////////////////////////////////////////////////////////////////////////////////
+
+`ifdef DUALCORES
+
 module os2wb_dual(
     input              clk,
@@ -181 +184 @@
 );
 */
+
 pcx_fifo pcx_fifo_inst( 
     .clk(clk),
@@ -1121 +1125 @@
 );
 
-endmodule
+endmodule 
+
+`endif

trunk/sim/simula.do

@@ -1 @@
-#start with vsim -c -do simula.do
+#start with: vsim -c -do simula.do
 
 vlib work
@@ -32 +32 @@
 vlog  $env(XILINX)/../../verilog/src/glbl.v
 #vlog  $XILINX/../../verilog/src/glbl.v
-#vlog  ../sim/*.v
+vlog  ../sim/*.v
 
 #Pass the parameters for memory model parameter file#