source: XOpenSparcT1/trunk/sim/sim.do @ 10

Revision 10, 4.7 KB checked in by pntsvt00, 14 years ago (diff)

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[10]1###############################################################################
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34## Copyright 2007, 2008 Xilinx, Inc.
35## All rights reserved.
36##
37## This disclaimer and copyright notice must be retained as part
38## of this file at all times.
39###############################################################################
40##   ____  ____
41##  /   /\/   /
42## /___/  \  /    Vendor             : Xilinx
43## \   \   \/     Version            : 3.6
44##  \   \         Application        : MIG
45##  /   /         Filename           : sim.do
46## /___/   /\     Date Last Modified : $Date: 2010/06/29 12:03:41 $
47## \   \  /  \    Date Created       : Mon May 14 2007
48##  \___\/\___\
49##
50##Device: Virtex-5
51##Purpose:
52##    Sample sim .do file to compile and simulate memory interface
53##    design and run the simulation for specified period of time. Display the
54##    waveforms that are listed with "add wave" command.
55##    Assumptions:
56##      - Simulation takes place in \sim folder of MIG output directory
57##Reference:
58##Revision History:
59###############################################################################
60vlib work
61
62#Map the required libraries here.#
63
64#Compile all modules#
65vlog  ../rtl/ddr2_chipscope*
66vlog  ../rtl/*
67#Compile files in sim folder (excluding model parameter file)#
68#$XILINX variable must be set
69vlog  $env(XILINX)/verilog/src/glbl.v
70vlog  ../sim/*.v
71
72#Pass the parameters for memory model parameter file#
73vlog  +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model.v
74
75#Load the design. Use required libraries.#
76vsim -t ps -novopt +notimingchecks -L unisims_ver work.sim_tb_top glbl
77
78onerror {resume}
79#Log all the objects in design. These will appear in .wlf file#
80log -r /*
81#View sim_tb_top signals in waveform#
82add wave sim:/sim_tb_top/*
83
84#Change radix to Hexadecimal#
85radix hex
86#Supress Numeric Std package and Arith package warnings.#
87#For VHDL designs we get some warnings due to unknown values on some signals at startup#
88# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
89#We may also get some Arithmetic packeage warnings because of unknown values on#
90#some of the signals that are used in an Arithmetic operation.#
91#In order to suppress these warnings, we use following two commands#
92set NumericStdNoWarnings 1
93set StdArithNoWarnings 1
94
95#Choose simulation run time by inserting a breakpoint and then run for specified #
96#period. For more details, refer to Simulation Guide section of MIG user guide (UG086).#
97when {/sim_tb_top/phy_init_done = 1} {
98if {[when -label a_100] == ""} {
99when -label a_100 { $now = 50 us } {
100nowhen a_100
101report simulator control
102report simulator state
103if {[examine /sim_tb_top/error] == 0} {
104echo "TEST PASSED"
105stop
106}
107if {[examine /sim_tb_top/error] != 0} {
108echo "TEST FAILED: DATA ERROR"
109stop
110}
111}
112}
113}
114
115#In case calibration fails to complete, choose the run time and then stop#
116when {$now = @500 us and /sim_tb_top/phy_init_done != 1} {
117echo "TEST FAILED: CALIBRATION DID NOT COMPLETE"
118stop
119}
120
121echo "NOTE: Initial 200us power on period is skipped for simulation.
122      Change SIM_ONLY parameter in sim_tb_top file to activate this."
123
124run -all
125stop
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