source: XOpenSparcT1/trunk/sim/wiredly.vhd @ 10

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--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version            : 3.6
--  \   \        Application        : MIG
--  /   /        Filename           : wiredly.vhd
-- /___/   /\    Date Last Modified : $Date: 2010/06/29 12:03:42 $
-- \   \  /  \   Date Created       : Mon Jun 18 2007
--  \___\/\___\
--
-- Device      : Virtex-5
-- Design Name : DDR2
-- Description: This module provide
--   the definition of a zero ohm component (A, B).
--
--   The applications of this component include:
--     . Normal operation of a jumper wire (data flowing in both directions)
--
--   The component consists of 2 ports:
--      . Port A: One side of the pass-through switch
--      . Port B: The other side of the pass-through switch

--   The model is sensitive to transactions on all ports.  Once a
--   transaction is detected, all other transactions are ignored
--   for that simulation time (i.e. further transactions in that
--   delta time are ignored).
--
-- Model Limitations and Restrictions:
--   Signals asserted on the ports of the error injector should not have
--   transactions occuring in multiple delta times because the model
--   is sensitive to transactions on port A, B ONLY ONCE during
--   a simulation time.  Thus, once fired, a process will
--   not refire if there are multiple transactions occuring in delta times.
--   This condition may occur in gate level simulations with
--   ZERO delays because transactions may occur in multiple delta times.
--*****************************************************************************

library IEEE;
  use IEEE.Std_Logic_1164.all;

entity WireDelay is
  generic (
     Delay_g : time;
     Delay_rd : time);
  port
    (A     : inout Std_Logic;
     B     : inout Std_Logic;
     reset : in Std_Logic
     );
end WireDelay;


architecture WireDelay_a of WireDelay is

  signal A_r     : Std_Logic;
  signal B_r     : Std_Logic;
  signal line_en : Std_Logic;

begin

  A <= A_r;
  B <= B_r;

  ABC0_Lbl: process (reset, A, B)
  begin
    if (reset = '0') then
      line_en <= '0';
    else 
      if (A /= A_r) then
        line_en <= '0';
      elsif (B_r /= B) then
        line_en <= '1';
      else 
        line_en <= line_en;
      end if;
    end if;

  end process ABC0_Lbl;

 lnenab: process (reset, line_en, A, B)
   begin
    if (reset = '0') then
      A_r <= 'Z';
      B_r <= 'Z';
    elsif (line_en = '1') then
      A_r <= TRANSPORT B AFTER Delay_rd;
      B_r <= 'Z';
    else 
      B_r <= TRANSPORT A AFTER Delay_g;
      A_r <= 'Z';
    end if;
   end process;

end WireDelay_a;