| [6] | 1 | #-- Synopsys, Inc. |
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| 2 | #-- Version E-2010.09-SP3 |
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| 3 | #-- Project file /home/sal/Desktop/sparc64soc/synplicity/proj_1.prj |
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| 4 | |
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| 5 | #project files |
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| [10] | 6 | add_file -verilog "../T1-common/include/xst_defines.h" |
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| 7 | add_file -verilog "../Top/W1.v" |
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| 8 | add_file -verilog "../OC-UART/raminfr.v" |
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| 9 | add_file -verilog "../OC-UART/timescale.v" |
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| 10 | add_file -verilog "../OC-UART/uart_debug_if.v" |
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| 11 | add_file -verilog "../OC-UART/uart_defines.v" |
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| 12 | add_file -verilog "../OC-UART/uart_receiver.v" |
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| 13 | add_file -verilog "../OC-UART/uart_regs.v" |
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| 14 | add_file -verilog "../OC-UART/uart_rfifo.v" |
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| 15 | add_file -verilog "../OC-UART/uart_sync_flops.v" |
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| 16 | add_file -verilog "../OC-UART/uart_tfifo.v" |
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| 17 | add_file -verilog "../OC-UART/uart_top.v" |
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| 18 | add_file -verilog "../OC-UART/uart_transmitter.v" |
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| 19 | add_file -verilog "../OC-UART/uart_wb.v" |
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| 20 | add_file -verilog "../NOR-flash/WBFLASH.v" |
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| 21 | add_file -verilog "../os2wb/l1ddir.v" |
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| 22 | add_file -verilog "../os2wb/l1dir.v" |
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| 23 | add_file -verilog "../os2wb/l1idir.v" |
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| 24 | add_file -verilog "../os2wb/os2wb.v" |
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| 25 | add_file -verilog "../os2wb/os2wb_dual.v" |
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| 26 | add_file -verilog "../os2wb/rst_ctrl.v" |
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| 27 | add_file -verilog "../os2wb/s1_top.v" |
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| 28 | add_file -verilog "../T1-common/common/cluster_header.v" |
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| 29 | add_file -verilog "../T1-common/common/cluster_header_ctu.v" |
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| 30 | add_file -verilog "../T1-common/common/cluster_header_dup.v" |
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| 31 | add_file -verilog "../T1-common/common/cluster_header_sync.v" |
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| 32 | add_file -verilog "../T1-common/common/cmp_sram_redhdr.v" |
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| 33 | add_file -verilog "../T1-common/common/dbl_buf.v" |
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| 34 | add_file -verilog "../T1-common/common/swrvr_clib.v" |
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| 35 | add_file -verilog "../T1-common/common/swrvr_dlib.v" |
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| 36 | add_file -verilog "../T1-common/common/sync_pulse_synchronizer.v" |
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| 37 | add_file -verilog "../T1-common/common/synchronizer_asr.v" |
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| 38 | add_file -verilog "../T1-common/common/synchronizer_asr_dup.v" |
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| 39 | add_file -verilog "../T1-common/common/test_stub_bist.v" |
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| 40 | add_file -verilog "../T1-common/common/test_stub_scan.v" |
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| 41 | add_file -verilog "../T1-common/common/ucb_bus_in.v" |
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| 42 | add_file -verilog "../T1-common/common/ucb_bus_out.v" |
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| 43 | add_file -verilog "../T1-common/common/ucb_flow_2buf.v" |
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| 44 | add_file -verilog "../T1-common/common/ucb_flow_jbi.v" |
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| 45 | add_file -verilog "../T1-common/common/ucb_flow_spi.v" |
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| 46 | add_file -verilog "../T1-common/common/ucb_noflow.v" |
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| 47 | add_file -verilog "../T1-common/m1/m1.V" |
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| 48 | add_file -verilog "../T1-common/srams/bw_r_cm16x40.v" |
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| 49 | add_file -verilog "../T1-common/srams/bw_r_cm16x40b.v" |
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| 50 | add_file -verilog "../T1-common/srams/bw_r_dcd.v" |
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| 51 | add_file -verilog "../T1-common/srams/bw_r_dcm.v" |
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| 52 | add_file -verilog "../T1-common/srams/bw_r_efa.v" |
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| 53 | add_file -verilog "../T1-common/srams/bw_r_frf.v" |
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| 54 | add_file -verilog "../T1-common/srams/bw_r_icd.v" |
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| 55 | add_file -verilog "../T1-common/srams/bw_r_idct.v" |
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| 56 | add_file -verilog "../T1-common/srams/bw_r_irf.v" |
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| 57 | add_file -verilog "../T1-common/srams/bw_r_irf_fpga1.v" |
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| 58 | add_file -verilog "../T1-common/srams/bw_r_irf_register.v" |
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| 59 | add_file -verilog "../T1-common/srams/bw_r_l2d.v" |
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| 60 | add_file -verilog "../T1-common/srams/bw_r_l2d_32k.v" |
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| 61 | add_file -verilog "../T1-common/srams/bw_r_l2d_rep_bot.v" |
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| 62 | add_file -verilog "../T1-common/srams/bw_r_l2d_rep_top.v" |
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| 63 | add_file -verilog "../T1-common/srams/bw_r_l2t.v" |
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| 64 | add_file -verilog "../T1-common/srams/bw_r_rf16x128d.v" |
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| 65 | add_file -verilog "../T1-common/srams/bw_r_rf16x160.v" |
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| 66 | add_file -verilog "../T1-common/srams/bw_r_rf16x32.v" |
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| 67 | add_file -verilog "../T1-common/srams/bw_r_rf32x108.v" |
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| 68 | add_file -verilog "../T1-common/srams/bw_r_rf32x152b.v" |
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| 69 | add_file -verilog "../T1-common/srams/bw_r_rf32x80.v" |
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| 70 | add_file -verilog "../T1-common/srams/bw_r_scm.v" |
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| 71 | add_file -verilog "../T1-common/srams/bw_r_tlb.v" |
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| 72 | add_file -verilog "../T1-common/srams/bw_r_tlb_fpga.v" |
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| 73 | add_file -verilog "../T1-common/srams/bw_rf_16x65.v" |
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| 74 | add_file -verilog "../T1-common/srams/bw_rf_16x81.v" |
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| 75 | add_file -verilog "../T1-common/srams/regfile_1w_4r.v" |
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| 76 | add_file -verilog "../T1-common/u1/u1.V" |
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| 77 | add_file -verilog "../T1-FPU/bw_clk_cl_fpu_cmp.v" |
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| 78 | add_file -verilog "../T1-FPU/fpu.v" |
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| 79 | add_file -verilog "../T1-FPU/fpu_add.v" |
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| 80 | add_file -verilog "../T1-FPU/fpu_add_ctl.v" |
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| 81 | add_file -verilog "../T1-FPU/fpu_add_exp_dp.v" |
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| 82 | add_file -verilog "../T1-FPU/fpu_add_frac_dp.v" |
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| 83 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_53b.v" |
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| 84 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_64b.v" |
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| 85 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_lvl1.v" |
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| 86 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_lvl2.v" |
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| 87 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_lvl3.v" |
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| 88 | add_file -verilog "../T1-FPU/fpu_cnt_lead0_lvl4.v" |
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| 89 | add_file -verilog "../T1-FPU/fpu_denorm_3b.v" |
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| 90 | add_file -verilog "../T1-FPU/fpu_denorm_3to1.v" |
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| 91 | add_file -verilog "../T1-FPU/fpu_denorm_frac.v" |
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| 92 | add_file -verilog "../T1-FPU/fpu_div.v" |
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| 93 | add_file -verilog "../T1-FPU/fpu_div_ctl.v" |
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| 94 | add_file -verilog "../T1-FPU/fpu_div_exp_dp.v" |
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| 95 | add_file -verilog "../T1-FPU/fpu_div_frac_dp.v" |
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| 96 | add_file -verilog "../T1-FPU/fpu_in.v" |
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| 97 | add_file -verilog "../T1-FPU/fpu_in2_gt_in1_2b.v" |
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| 98 | add_file -verilog "../T1-FPU/fpu_in2_gt_in1_3b.v" |
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| 99 | add_file -verilog "../T1-FPU/fpu_in2_gt_in1_3to1.v" |
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| 100 | add_file -verilog "../T1-FPU/fpu_in2_gt_in1_frac.v" |
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| 101 | add_file -verilog "../T1-FPU/fpu_in_ctl.v" |
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| 102 | add_file -verilog "../T1-FPU/fpu_in_dp.v" |
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| 103 | add_file -verilog "../T1-FPU/fpu_mul.v" |
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| 104 | add_file -verilog "../T1-FPU/fpu_mul_ctl.v" |
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| 105 | add_file -verilog "../T1-FPU/fpu_mul_exp_dp.v" |
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| 106 | add_file -verilog "../T1-FPU/fpu_mul_frac_dp.v" |
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| 107 | add_file -verilog "../T1-FPU/fpu_out.v" |
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| 108 | add_file -verilog "../T1-FPU/fpu_out_ctl.v" |
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| 109 | add_file -verilog "../T1-FPU/fpu_out_dp.v" |
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| 110 | add_file -verilog "../T1-FPU/fpu_rptr_groups.v" |
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| 111 | add_file -verilog "../T1-FPU/fpu_rptr_macros.v" |
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| 112 | add_file -verilog "../T1-FPU/fpu_rptr_min_global.v" |
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| 113 | add_file -verilog "../WB/wb_conbus_arb.v" |
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| 114 | add_file -verilog "../WB/wb_conbus_defines.v" |
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| 115 | add_file -verilog "../WB/wb_conbus_top.v" |
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| 116 | add_file -verilog "../WB2ALTDDR3/dram_wb.v" |
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| 117 | add_file -verilog "../Xilinx/cachedir.v" |
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| [28] | 118 | add_file -verilog "../Xilinx/dram_fifo_fall.v" |
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| [10] | 119 | add_file -verilog "../Xilinx/dram_fifo.v" |
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| 120 | add_file -verilog "../Xilinx/pcx_fifo.v" |
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| 121 | add_file -verilog "../Xilinx/dram.v" |
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| 122 | add_file -verilog "../Xilinx/ddr2_chipscope.v" |
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| 123 | add_file -verilog "../Xilinx/ddr2_ctrl.v" |
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| 124 | add_file -verilog "../Xilinx/ddr2_idelay_ctrl.v" |
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| 125 | add_file -verilog "../Xilinx/ddr2_infrastructure.v" |
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| 126 | add_file -verilog "../Xilinx/ddr2_mem_if_top.v" |
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| 127 | add_file -verilog "../Xilinx/ddr2_phy_calib.v" |
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| 128 | add_file -verilog "../Xilinx/ddr2_phy_ctl_io.v" |
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| 129 | add_file -verilog "../Xilinx/ddr2_phy_dm_iob.v" |
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| 130 | add_file -verilog "../Xilinx/ddr2_phy_dq_iob.v" |
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| 131 | add_file -verilog "../Xilinx/ddr2_phy_dqs_iob.v" |
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| 132 | add_file -verilog "../Xilinx/ddr2_phy_init.v" |
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| 133 | #add_file -vhdl -lib work "../Xilinx/ddr2_phy_init.vhd" |
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| 134 | add_file -verilog "../Xilinx/ddr2_phy_io.v" |
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| 135 | #add_file -vhdl -lib work "../Xilinx/ddr2_phy_io.vhd" |
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| 136 | add_file -verilog "../Xilinx/ddr2_phy_top.v" |
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| 137 | #add_file -vhdl -lib work "../Xilinx/ddr2_phy_top.vhd" |
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| 138 | add_file -verilog "../Xilinx/ddr2_phy_write.v" |
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| 139 | #add_file -vhdl -lib work "../Xilinx/ddr2_phy_write.vhd" |
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| 140 | add_file -verilog "../Xilinx/ddr2_top.v" |
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| 141 | add_file -verilog "../Xilinx/ddr2_usr_addr_fifo.v" |
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| 142 | add_file -verilog "../Xilinx/ddr2_usr_rd.v" |
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| 143 | add_file -verilog "../Xilinx/ddr2_usr_top.v" |
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| 144 | add_file -verilog "../Xilinx/ddr2_usr_wr.v" |
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| 145 | add_file -verilog "../T1-CPU/exu/sparc_exu.v" |
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| 146 | add_file -verilog "../T1-CPU/exu/sparc_exu_alu.v" |
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| 147 | add_file -verilog "../T1-CPU/exu/sparc_exu_alu_16eql.v" |
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| 148 | add_file -verilog "../T1-CPU/exu/sparc_exu_aluadder64.v" |
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| 149 | add_file -verilog "../T1-CPU/exu/sparc_exu_aluaddsub.v" |
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| 150 | add_file -verilog "../T1-CPU/exu/sparc_exu_alulogic.v" |
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| 151 | add_file -verilog "../T1-CPU/exu/sparc_exu_aluor32.v" |
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| 152 | add_file -verilog "../T1-CPU/exu/sparc_exu_aluspr.v" |
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| 153 | add_file -verilog "../T1-CPU/exu/sparc_exu_aluzcmp64.v" |
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| 154 | add_file -verilog "../T1-CPU/exu/sparc_exu_byp.v" |
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| 155 | add_file -verilog "../T1-CPU/exu/sparc_exu_byp_eccgen.v" |
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| 156 | add_file -verilog "../T1-CPU/exu/sparc_exu_div.v" |
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| 157 | add_file -verilog "../T1-CPU/exu/sparc_exu_div_32eql.v" |
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| 158 | add_file -verilog "../T1-CPU/exu/sparc_exu_div_yreg.v" |
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| 159 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecc.v" |
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| 160 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecc_dec.v" |
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| 161 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl.v" |
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| 162 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl_cnt6.v" |
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| 163 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl_divcntl.v" |
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| 164 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl_eccctl.v" |
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| 165 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl_mdqctl.v" |
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| 166 | add_file -verilog "../T1-CPU/exu/sparc_exu_ecl_wb.v" |
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| 167 | add_file -verilog "../T1-CPU/exu/sparc_exu_eclbyplog.v" |
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| 168 | add_file -verilog "../T1-CPU/exu/sparc_exu_eclbyplog_rs1.v" |
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| 169 | add_file -verilog "../T1-CPU/exu/sparc_exu_eclccr.v" |
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| 170 | add_file -verilog "../T1-CPU/exu/sparc_exu_eclcomp7.v" |
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| 171 | add_file -verilog "../T1-CPU/exu/sparc_exu_reg.v" |
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| 172 | add_file -verilog "../T1-CPU/exu/sparc_exu_rml.v" |
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| 173 | add_file -verilog "../T1-CPU/exu/sparc_exu_rml_cwp.v" |
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| 174 | add_file -verilog "../T1-CPU/exu/sparc_exu_rml_inc3.v" |
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| 175 | add_file -verilog "../T1-CPU/exu/sparc_exu_rndrob.v" |
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| 176 | add_file -verilog "../T1-CPU/exu/sparc_exu_shft.v" |
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| 177 | add_file -verilog "../T1-CPU/ffu/sparc_ffu.v" |
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| 178 | add_file -verilog "../T1-CPU/ffu/sparc_ffu_ctl.v" |
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| 179 | add_file -verilog "../T1-CPU/ffu/sparc_ffu_ctl_visctl.v" |
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| 180 | add_file -verilog "../T1-CPU/ffu/sparc_ffu_dp.v" |
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| 181 | add_file -verilog "../T1-CPU/ffu/sparc_ffu_part_add32.v" |
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| 182 | add_file -verilog "../T1-CPU/ffu/sparc_ffu_vis.v" |
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| 183 | add_file -verilog "../T1-CPU/ifu/sparc_ifu.v" |
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| 184 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_cmp35.v" |
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| 185 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_ctr5.v" |
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| 186 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_dcl.v" |
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| 187 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_dec.v" |
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| 188 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_errctl.v" |
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| 189 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_errdp.v" |
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| 190 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_fcl.v" |
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| 191 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_fdp.v" |
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| 192 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_ifqctl.v" |
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| 193 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_ifqdp.v" |
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| 194 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_imd.v" |
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| 195 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_incr46.v" |
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| 196 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_invctl.v" |
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| 197 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_lfsr5.v" |
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| 198 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_lru4.v" |
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| 199 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_mbist.v" |
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| 200 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_milfsm.v" |
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| 201 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_par16.v" |
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| 202 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_par32.v" |
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| 203 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_par34.v" |
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| 204 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_rndrob.v" |
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| 205 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_sscan.v" |
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| 206 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_swl.v" |
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| 207 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_swpla.v" |
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| 208 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_thrcmpl.v" |
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| 209 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_thrfsm.v" |
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| 210 | add_file -verilog "../T1-CPU/ifu/sparc_ifu_wseldp.v" |
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| 211 | add_file -verilog "../T1-CPU/lsu/lsu.v" |
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| 212 | add_file -verilog "../T1-CPU/lsu/lsu_asi_decode.v" |
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| 213 | add_file -verilog "../T1-CPU/lsu/lsu_dc_parity_gen.v" |
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| 214 | add_file -verilog "../T1-CPU/lsu/lsu_dcache_lfsr.v" |
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| 215 | add_file -verilog "../T1-CPU/lsu/lsu_dcdp.v" |
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| 216 | add_file -verilog "../T1-CPU/lsu/lsu_dctl.v" |
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| 217 | add_file -verilog "../T1-CPU/lsu/lsu_dctldp.v" |
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| 218 | add_file -verilog "../T1-CPU/lsu/lsu_excpctl.v" |
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| 219 | add_file -verilog "../T1-CPU/lsu/lsu_pcx_qmon.v" |
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| 220 | add_file -verilog "../T1-CPU/lsu/lsu_qctl1.v" |
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| 221 | add_file -verilog "../T1-CPU/lsu/lsu_qctl2.v" |
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| 222 | add_file -verilog "../T1-CPU/lsu/lsu_qdp1.v" |
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| 223 | add_file -verilog "../T1-CPU/lsu/lsu_qdp2.v" |
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| 224 | add_file -verilog "../T1-CPU/lsu/lsu_rrobin_picker2.v" |
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| 225 | add_file -verilog "../T1-CPU/lsu/lsu_stb_ctl.v" |
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| 226 | add_file -verilog "../T1-CPU/lsu/lsu_stb_ctldp.v" |
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| 227 | add_file -verilog "../T1-CPU/lsu/lsu_stb_rwctl.v" |
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| 228 | add_file -verilog "../T1-CPU/lsu/lsu_stb_rwdp.v" |
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| 229 | add_file -verilog "../T1-CPU/lsu/lsu_tagdp.v" |
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| 230 | add_file -verilog "../T1-CPU/lsu/lsu_tlbdp.v" |
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| 231 | add_file -verilog "../T1-CPU/mul/mul64.v" |
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| 232 | add_file -verilog "../T1-CPU/mul/sparc_mul_cntl.v" |
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| 233 | add_file -verilog "../T1-CPU/mul/sparc_mul_dp.v" |
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| 234 | add_file -verilog "../T1-CPU/mul/sparc_mul_top.v" |
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| 235 | add_file -verilog "../T1-CPU/rtl/bw_clk_cl_sparc_cmp.v" |
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| 236 | add_file -verilog "../T1-CPU/rtl/cpx_spc_buf.v" |
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| 237 | add_file -verilog "../T1-CPU/rtl/cpx_spc_rpt.v" |
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| 238 | add_file -verilog "../T1-CPU/rtl/sparc.v" |
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| 239 | add_file -verilog "../T1-CPU/rtl/spc_pcx_buf.v" |
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| 240 | add_file -verilog "../T1-CPU/spu/spu.v" |
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| 241 | add_file -verilog "../T1-CPU/spu/spu_ctl.v" |
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| 242 | add_file -verilog "../T1-CPU/spu/spu_lsurpt.v" |
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| 243 | add_file -verilog "../T1-CPU/spu/spu_lsurpt1.v" |
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| 244 | add_file -verilog "../T1-CPU/spu/spu_maaddr.v" |
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| 245 | add_file -verilog "../T1-CPU/spu/spu_maaeqb.v" |
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| 246 | add_file -verilog "../T1-CPU/spu/spu_mactl.v" |
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| 247 | add_file -verilog "../T1-CPU/spu/spu_madp.v" |
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| 248 | add_file -verilog "../T1-CPU/spu/spu_maexp.v" |
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| 249 | add_file -verilog "../T1-CPU/spu/spu_mald.v" |
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| 250 | add_file -verilog "../T1-CPU/spu/spu_mamul.v" |
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| 251 | add_file -verilog "../T1-CPU/spu/spu_mared.v" |
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| 252 | add_file -verilog "../T1-CPU/spu/spu_mast.v" |
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| 253 | add_file -verilog "../T1-CPU/spu/spu_wen.v" |
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| 254 | add_file -verilog "../T1-CPU/tlu/sparc_tlu_dec64.v" |
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| 255 | add_file -verilog "../T1-CPU/tlu/sparc_tlu_intctl.v" |
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| 256 | add_file -verilog "../T1-CPU/tlu/sparc_tlu_intdp.v" |
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| 257 | add_file -verilog "../T1-CPU/tlu/sparc_tlu_penc64.v" |
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| 258 | add_file -verilog "../T1-CPU/tlu/sparc_tlu_zcmp64.v" |
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| 259 | add_file -verilog "../T1-CPU/tlu/tlu.v" |
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| 260 | add_file -verilog "../T1-CPU/tlu/tlu_addern_32.v" |
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| 261 | add_file -verilog "../T1-CPU/tlu/tlu_hyperv.v" |
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| 262 | add_file -verilog "../T1-CPU/tlu/tlu_incr64.v" |
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| 263 | add_file -verilog "../T1-CPU/tlu/tlu_misctl.v" |
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| 264 | add_file -verilog "../T1-CPU/tlu/tlu_mmu_ctl.v" |
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| 265 | add_file -verilog "../T1-CPU/tlu/tlu_mmu_dp.v" |
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| 266 | add_file -verilog "../T1-CPU/tlu/tlu_pib.v" |
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| 267 | add_file -verilog "../T1-CPU/tlu/tlu_prencoder16.v" |
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| 268 | add_file -verilog "../T1-CPU/tlu/tlu_rrobin_picker.v" |
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| 269 | add_file -verilog "../T1-CPU/tlu/tlu_tcl.v" |
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| 270 | add_file -verilog "../T1-CPU/tlu/tlu_tdp.v" |
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| 271 | add_file -verilog "../Xilinx/pll.v" |
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| [6] | 272 | |
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| 273 | |
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| 274 | #implementation: "rev_1" |
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| 275 | impl -add rev_1 -type fpga |
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| 276 | |
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| 277 | # |
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| 278 | #implementation attributes |
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| 279 | |
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| 280 | set_option -vlog_std v2001 |
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| 281 | set_option -project_relative_includes 1 |
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| 282 | set_option -enable_nfilter 0 |
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| 283 | set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/ |
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| 284 | |
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| [8] | 285 | #pr_1 attributes |
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| 286 | set_option -job pr_1 -add par |
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| 287 | set_option -job pr_1 -option enable_run 1 |
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| 288 | set_option -job pr_1 -option run_backannotation 0 |
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| 289 | |
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| [6] | 290 | #device options |
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| 291 | set_option -technology Virtex5 |
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| [8] | 292 | set_option -part XC5VLX110T |
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| 293 | set_option -package FF1136 |
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| [6] | 294 | set_option -speed_grade -1 |
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| 295 | set_option -part_companion "" |
|---|
| 296 | |
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| 297 | #compilation/mapping options |
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| 298 | set_option -use_fsm_explorer 0 |
|---|
| 299 | set_option -top_module "W1" |
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| 300 | |
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| 301 | # mapper_options |
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| 302 | set_option -frequency auto |
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| 303 | set_option -write_verilog 0 |
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| 304 | set_option -write_vhdl 0 |
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| 305 | |
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| 306 | # Xilinx Virtex2 |
|---|
| 307 | set_option -run_prop_extract 1 |
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| 308 | set_option -maxfan 10000 |
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| 309 | set_option -disable_io_insertion 0 |
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| 310 | set_option -pipe 1 |
|---|
| 311 | set_option -update_models_cp 0 |
|---|
| 312 | set_option -retiming 0 |
|---|
| 313 | set_option -no_sequential_opt 0 |
|---|
| 314 | set_option -fixgatedclocks 3 |
|---|
| 315 | set_option -fixgeneratedclocks 3 |
|---|
| 316 | |
|---|
| 317 | # Xilinx Virtex5 |
|---|
| 318 | set_option -enable_prepacking 1 |
|---|
| 319 | |
|---|
| 320 | # NFilter |
|---|
| 321 | set_option -popfeed 0 |
|---|
| 322 | set_option -constprop 0 |
|---|
| 323 | set_option -createhierarchy 0 |
|---|
| 324 | |
|---|
| 325 | # sequential_optimization_options |
|---|
| 326 | set_option -symbolic_fsm_compiler 1 |
|---|
| 327 | |
|---|
| 328 | # Compiler Options |
|---|
| 329 | set_option -compiler_compatible 0 |
|---|
| 330 | set_option -resource_sharing 1 |
|---|
| 331 | |
|---|
| 332 | #VIF options |
|---|
| 333 | set_option -write_vif 1 |
|---|
| 334 | |
|---|
| 335 | #automatic place and route (vendor) options |
|---|
| 336 | set_option -write_apr_constraint 1 |
|---|
| 337 | |
|---|
| 338 | #set result format/file last |
|---|
| 339 | project -result_file "./rev_1/W1.edf" |
|---|
| 340 | |
|---|
| 341 | #design plan options |
|---|
| 342 | set_option -nfilter_user_path "" |
|---|
| 343 | impl -active "rev_1" |
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