Changeset 8 in XOpenSparcT1 for trunk/synplicity/proj_1.prj


Ignore:
Timestamp:
03/22/11 11:51:17 (14 years ago)
Author:
pntsvt00
Message:

modifiche per la sintesi su Xilinx

File:
1 edited

Legend:

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Added
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  • trunk/synplicity/proj_1.prj

    r6 r8  
    44 
    55#project files 
     6add_file -verilog "../trunk/T1-common/include/xst_defines.h" 
    67add_file -verilog "../trunk/Top/W1.v" 
    78add_file -verilog "../trunk/OC-UART/raminfr.v" 
    … …  
    279280set_option -project_relative_includes 1 
    280281set_option -enable_nfilter 0 
    281 set_option -hdl_define -set "FPGA FPGA_SYN" 
    282282set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/ 
     283 
     284#pr_1 attributes 
     285set_option -job pr_1 -add par 
     286set_option -job pr_1 -option enable_run 1 
     287set_option -job pr_1 -option run_backannotation 0 
    283288 
    284289#device options 
    285290set_option -technology Virtex5 
    286 set_option -part XC5VLX20T 
    287 set_option -package FF323 
     291set_option -part XC5VLX110T 
     292set_option -package FF1136 
    288293set_option -speed_grade -1 
    289294set_option -part_companion "" 
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