Changeset 8 in XOpenSparcT1
- Timestamp:
- 03/22/11 11:51:17 (14 years ago)
- Location:
- trunk
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/NOR-flash/WBFLASH.v
r6 r8 47 47 input wb1_cab_i, 48 48 49 output reg [2 4:0] flash_addr,49 output reg [21:0] flash_addr, 50 50 input [15:0] flash_data, 51 51 output flash_oen, 52 52 output flash_wen, 53 output flash_cen ,54 input [ 1:0] flash_rev53 output flash_cen 54 //input [ 1:0] flash_rev 55 55 //output flash_ldn 56 56 ); … … 132 132 assign wb1_dat_o=wb1_dat; 133 133 134 wire [1:0] flash_rev_d;134 //wire [1:0] flash_rev_d; 135 135 136 assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d;136 //assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d; 137 137 138 always @( * )138 /*always @( * ) 139 139 case({wb1_stb_i,flash_rev_d}) 140 140 3'b000:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000; … … 146 146 3'b110:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000; 147 147 3'b111:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000; 148 endcase 148 endcase*/ 149 150 always @( * ) 151 if (wb1_stb_i) 152 flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0400000; 153 else 154 flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000; 149 155 150 156 assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1); -
trunk/Top/W1.v
r6 r8 22 22 module W1( 23 23 24 input sysclk,24 input clk_in, 25 25 input sysrst, 26 26 … … 42 42 output [ 7:0] ddr3_dm, 43 43 44 output phy_init_done, // LED45 input rup,46 input rdn,44 //output phy_init_done, // LED 45 //input rup, 46 //input rdn, 47 47 48 48 // Console interface 49 49 input srx, 50 50 output stx, 51 input [1:0] flash_rev,51 //input [1:0] flash_rev, 52 52 53 53 /* MII interface replaced by SGMII … … 80 80 //output led_an, 81 81 82 output [2 4:0] flash_addr,82 output [21:0] flash_addr, 83 83 input [15:0] flash_data, 84 84 output flash_oen, … … 90 90 ); 91 91 92 wire pllclk; 93 wire sysclk; 92 94 wire wb_rst_i; 93 95 wire [35:0] CONTROL0; … … 387 389 dram_wb dram_wb_inst ( 388 390 .clk200(sysclk), 389 .rup(rup), 390 .rdn(rdn), 391 //.clk200(clk_in), 392 //.rup(rup), 393 //.rdn(rdn), 391 394 .wb_clk_i(wb_clk_i), 392 395 .wb_rst_i(wb_rst_i), … … 455 458 .flash_oen(flash_oen), 456 459 .flash_wen(flash_wen), 457 .flash_cen(flash_cen) ,458 .flash_rev(flash_rev)460 .flash_cen(flash_cen) 461 //.flash_rev(flash_rev) 459 462 ); 460 463 … … 570 573 assign sysrst_p=!sysrst; 571 574 575 576 IBUFG ibufg_inst (.O(sysclk),.I(clk_in)); 577 BUFG bufg_inst (.O(pllclk),.I(sysclk)); 578 572 579 // Standard PLL 573 580 pll pll_inst( 574 581 .RST_IN(sysrst_p), 575 .CLKIN1_IN( sysclk),582 .CLKIN1_IN(pllclk), 576 583 .CLKOUT0_OUT(wb_clk_i), //Up to 75 MHz on Stratix IV 577 584 .LOCKED_OUT(dcm_locked) -
trunk/synplicity/proj_1.prj
r6 r8 4 4 5 5 #project files 6 add_file -verilog "../trunk/T1-common/include/xst_defines.h" 6 7 add_file -verilog "../trunk/Top/W1.v" 7 8 add_file -verilog "../trunk/OC-UART/raminfr.v" … … 279 280 set_option -project_relative_includes 1 280 281 set_option -enable_nfilter 0 281 set_option -hdl_define -set "FPGA FPGA_SYN"282 282 set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/ 283 284 #pr_1 attributes 285 set_option -job pr_1 -add par 286 set_option -job pr_1 -option enable_run 1 287 set_option -job pr_1 -option run_backannotation 0 283 288 284 289 #device options 285 290 set_option -technology Virtex5 286 set_option -part XC5VLX 20T287 set_option -package FF 323291 set_option -part XC5VLX110T 292 set_option -package FF1136 288 293 set_option -speed_grade -1 289 294 set_option -part_companion ""
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