Changeset 8 in XOpenSparcT1

Timestamp:

03/22/11 11:51:17 (13 years ago)

Author:

pntsvt00

Message:

modifiche per la sintesi su Xilinx

Location:

trunk

Files:

• NOR-flash/WBFLASH.v (modified) (3 diffs)
• Top/W1.v (modified) (7 diffs)
• synplicity/proj_1.prj (modified) (2 diffs)

trunk/NOR-flash/WBFLASH.v

@@ -47 +47 @@
     input             wb1_cab_i,
 
-    output reg [24:0] flash_addr,
+    output reg [21:0] flash_addr,
     input      [15:0] flash_data,
     output            flash_oen,
     output            flash_wen,
-    output            flash_cen,
-    input      [ 1:0] flash_rev
+    output            flash_cen
+    //input      [ 1:0] flash_rev
      //output            flash_ldn
 );
@@ -132 +132 @@
 assign wb1_dat_o=wb1_dat;
 
-wire [1:0] flash_rev_d;
+//wire [1:0] flash_rev_d;
 
-assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d;
+//assign flash_rev_d=wb_rst_i ? flash_rev:flash_rev_d;
 
-always @( * )
+/*always @( * )
    case({wb1_stb_i,flash_rev_d})
       3'b000:flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000;
@@ -146 +146 @@
       3'b110:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
       3'b111:flash_addr<={wb1_adr_i[25:3],wordcnt}+25'h0400000;
-   endcase
+   endcase*/
+
+always @( * )
+ if (wb1_stb_i)
+      flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0400000;
+ else   
+      flash_addr<={wb_adr_i[25:3],wordcnt}+25'h0000000;
 
 assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1);

trunk/Top/W1.v

@@ -22 +22 @@
 module W1(
 
-   input         sysclk,
+   input         clk_in,
    input         sysrst,
 
@@ -42 +42 @@
    output [ 7:0] ddr3_dm,
 
-   output        phy_init_done, // LED
-   input         rup,
-   input         rdn,
+   //output        phy_init_done, // LED
+   //input         rup,
+   //input         rdn,
         
    // Console interface
    input  srx,
    output stx,
-   input  [1:0] flash_rev,
+   //input  [1:0] flash_rev,
    
    /* MII interface replaced by SGMII
@@ -80 +80 @@
    //output led_an,
         
-   output     [24:0] flash_addr,
+   output     [21:0] flash_addr,
    input      [15:0] flash_data,
    output            flash_oen,
@@ -90 +90 @@
 );
 
+wire pllclk;
+wire sysclk;
 wire wb_rst_i;
 wire [35:0] CONTROL0;
@@ -387 +389 @@
 dram_wb dram_wb_inst (
     .clk200(sysclk), 
-    .rup(rup),
-    .rdn(rdn),
+    //.clk200(clk_in),
+    //.rup(rup),
+    //.rdn(rdn),
     .wb_clk_i(wb_clk_i), 
     .wb_rst_i(wb_rst_i), 
@@ -455 +458 @@
     .flash_oen(flash_oen), 
     .flash_wen(flash_wen), 
-    .flash_cen(flash_cen),
-    .flash_rev(flash_rev)
+    .flash_cen(flash_cen)
+    //.flash_rev(flash_rev)
 );
 
@@ -570 +573 @@
 assign sysrst_p=!sysrst;
 
+
+IBUFG ibufg_inst (.O(sysclk),.I(clk_in));
+BUFG bufg_inst (.O(pllclk),.I(sysclk));
+
 // Standard PLL
 pll pll_inst(
         .RST_IN(sysrst_p),
-        .CLKIN1_IN(sysclk),
+        .CLKIN1_IN(pllclk),
         .CLKOUT0_OUT(wb_clk_i), //Up to 75 MHz on Stratix IV
         .LOCKED_OUT(dcm_locked)

trunk/synplicity/proj_1.prj

@@ -4 +4 @@
 
 #project files
+add_file -verilog "../trunk/T1-common/include/xst_defines.h"
 add_file -verilog "../trunk/Top/W1.v"
 add_file -verilog "../trunk/OC-UART/raminfr.v"
@@ -279 +280 @@
 set_option -project_relative_includes 1
 set_option -enable_nfilter 0
-set_option -hdl_define -set "FPGA FPGA_SYN"
 set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/
+
+#pr_1 attributes
+set_option -job pr_1 -add par
+set_option -job pr_1 -option enable_run 1
+set_option -job pr_1 -option run_backannotation 0
 
 #device options
 set_option -technology Virtex5
-set_option -part XC5VLX20T
-set_option -package FF323
+set_option -part XC5VLX110T
+set_option -package FF1136
 set_option -speed_grade -1
 set_option -part_companion ""