Changeset 8 in XOpenSparcT1 for trunk/Top/W1.v

Timestamp:

03/22/11 11:51:17 (14 years ago)

Author:

pntsvt00

Message:

modifiche per la sintesi su Xilinx

File:

• trunk/Top/W1.v (modified) (7 diffs)

trunk/Top/W1.v

@@ -22 +22 @@
 module W1(
 
-   input         sysclk,
+   input         clk_in,
    input         sysrst,
 
@@ -42 +42 @@
    output [ 7:0] ddr3_dm,
 
-   output        phy_init_done, // LED
-   input         rup,
-   input         rdn,
+   //output        phy_init_done, // LED
+   //input         rup,
+   //input         rdn,
         
    // Console interface
    input  srx,
    output stx,
-   input  [1:0] flash_rev,
+   //input  [1:0] flash_rev,
    
    /* MII interface replaced by SGMII
@@ -80 +80 @@
    //output led_an,
         
-   output     [24:0] flash_addr,
+   output     [21:0] flash_addr,
    input      [15:0] flash_data,
    output            flash_oen,
@@ -90 +90 @@
 );
 
+wire pllclk;
+wire sysclk;
 wire wb_rst_i;
 wire [35:0] CONTROL0;
@@ -387 +389 @@
 dram_wb dram_wb_inst (
     .clk200(sysclk), 
-    .rup(rup),
-    .rdn(rdn),
+    //.clk200(clk_in),
+    //.rup(rup),
+    //.rdn(rdn),
     .wb_clk_i(wb_clk_i), 
     .wb_rst_i(wb_rst_i), 
@@ -455 +458 @@
     .flash_oen(flash_oen), 
     .flash_wen(flash_wen), 
-    .flash_cen(flash_cen),
-    .flash_rev(flash_rev)
+    .flash_cen(flash_cen)
+    //.flash_rev(flash_rev)
 );
 
@@ -570 +573 @@
 assign sysrst_p=!sysrst;
 
+
+IBUFG ibufg_inst (.O(sysclk),.I(clk_in));
+BUFG bufg_inst (.O(pllclk),.I(sysclk));
+
 // Standard PLL
 pll pll_inst(
         .RST_IN(sysrst_p),
-        .CLKIN1_IN(sysclk),
+        .CLKIN1_IN(pllclk),
         .CLKOUT0_OUT(wb_clk_i), //Up to 75 MHz on Stratix IV
         .LOCKED_OUT(dcm_locked)