source: XOpenSparcT1/trunk/synplicity/proj_1.prj @ 6

Revision 6, 16.6 KB checked in by pntsvt00, 14 years ago (diff)

versione iniziale opensparc
Line 
1#-- Synopsys, Inc.
2#-- Version E-2010.09-SP3
3#-- Project file /home/sal/Desktop/sparc64soc/synplicity/proj_1.prj
4
5#project files
6add_file -verilog "../trunk/Top/W1.v"
7add_file -verilog "../trunk/OC-UART/raminfr.v"
8add_file -verilog "../trunk/OC-UART/timescale.v"
9add_file -verilog "../trunk/OC-UART/uart_debug_if.v"
10add_file -verilog "../trunk/OC-UART/uart_defines.v"
11add_file -verilog "../trunk/OC-UART/uart_receiver.v"
12add_file -verilog "../trunk/OC-UART/uart_regs.v"
13add_file -verilog "../trunk/OC-UART/uart_rfifo.v"
14add_file -verilog "../trunk/OC-UART/uart_sync_flops.v"
15add_file -verilog "../trunk/OC-UART/uart_tfifo.v"
16add_file -verilog "../trunk/OC-UART/uart_top.v"
17add_file -verilog "../trunk/OC-UART/uart_transmitter.v"
18add_file -verilog "../trunk/OC-UART/uart_wb.v"
19add_file -verilog "../trunk/NOR-flash/WBFLASH.v"
20add_file -verilog "../trunk/os2wb/l1ddir.v"
21add_file -verilog "../trunk/os2wb/l1dir.v"
22add_file -verilog "../trunk/os2wb/l1idir.v"
23add_file -verilog "../trunk/os2wb/os2wb.v"
24add_file -verilog "../trunk/os2wb/os2wb_dual.v"
25add_file -verilog "../trunk/os2wb/rst_ctrl.v"
26add_file -verilog "../trunk/os2wb/s1_top.v"
27add_file -verilog "../trunk/T1-common/common/cluster_header.v"
28add_file -verilog "../trunk/T1-common/common/cluster_header_ctu.v"
29add_file -verilog "../trunk/T1-common/common/cluster_header_dup.v"
30add_file -verilog "../trunk/T1-common/common/cluster_header_sync.v"
31add_file -verilog "../trunk/T1-common/common/cmp_sram_redhdr.v"
32add_file -verilog "../trunk/T1-common/common/dbl_buf.v"
33add_file -verilog "../trunk/T1-common/common/swrvr_clib.v"
34add_file -verilog "../trunk/T1-common/common/swrvr_dlib.v"
35add_file -verilog "../trunk/T1-common/common/sync_pulse_synchronizer.v"
36add_file -verilog "../trunk/T1-common/common/synchronizer_asr.v"
37add_file -verilog "../trunk/T1-common/common/synchronizer_asr_dup.v"
38add_file -verilog "../trunk/T1-common/common/test_stub_bist.v"
39add_file -verilog "../trunk/T1-common/common/test_stub_scan.v"
40add_file -verilog "../trunk/T1-common/common/ucb_bus_in.v"
41add_file -verilog "../trunk/T1-common/common/ucb_bus_out.v"
42add_file -verilog "../trunk/T1-common/common/ucb_flow_2buf.v"
43add_file -verilog "../trunk/T1-common/common/ucb_flow_jbi.v"
44add_file -verilog "../trunk/T1-common/common/ucb_flow_spi.v"
45add_file -verilog "../trunk/T1-common/common/ucb_noflow.v"
46add_file -verilog "../trunk/T1-common/m1/m1.V"
47add_file -verilog "../trunk/T1-common/srams/bw_r_cm16x40.v"
48add_file -verilog "../trunk/T1-common/srams/bw_r_cm16x40b.v"
49add_file -verilog "../trunk/T1-common/srams/bw_r_dcd.v"
50add_file -verilog "../trunk/T1-common/srams/bw_r_dcm.v"
51add_file -verilog "../trunk/T1-common/srams/bw_r_efa.v"
52add_file -verilog "../trunk/T1-common/srams/bw_r_frf.v"
53add_file -verilog "../trunk/T1-common/srams/bw_r_icd.v"
54add_file -verilog "../trunk/T1-common/srams/bw_r_idct.v"
55add_file -verilog "../trunk/T1-common/srams/bw_r_irf.v"
56add_file -verilog "../trunk/T1-common/srams/bw_r_irf_fpga1.v"
57add_file -verilog "../trunk/T1-common/srams/bw_r_irf_register.v"
58add_file -verilog "../trunk/T1-common/srams/bw_r_l2d.v"
59add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_32k.v"
60add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_rep_bot.v"
61add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_rep_top.v"
62add_file -verilog "../trunk/T1-common/srams/bw_r_l2t.v"
63add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x128d.v"
64add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x160.v"
65add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x32.v"
66add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x108.v"
67add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x152b.v"
68add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x80.v"
69add_file -verilog "../trunk/T1-common/srams/bw_r_scm.v"
70add_file -verilog "../trunk/T1-common/srams/bw_r_tlb.v"
71add_file -verilog "../trunk/T1-common/srams/bw_r_tlb_fpga.v"
72add_file -verilog "../trunk/T1-common/srams/bw_rf_16x65.v"
73add_file -verilog "../trunk/T1-common/srams/bw_rf_16x81.v"
74add_file -verilog "../trunk/T1-common/srams/regfile_1w_4r.v"
75add_file -verilog "../trunk/T1-common/u1/u1.V"
76add_file -verilog "../trunk/T1-FPU/bw_clk_cl_fpu_cmp.v"
77add_file -verilog "../trunk/T1-FPU/fpu.v"
78add_file -verilog "../trunk/T1-FPU/fpu_add.v"
79add_file -verilog "../trunk/T1-FPU/fpu_add_ctl.v"
80add_file -verilog "../trunk/T1-FPU/fpu_add_exp_dp.v"
81add_file -verilog "../trunk/T1-FPU/fpu_add_frac_dp.v"
82add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_53b.v"
83add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_64b.v"
84add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl1.v"
85add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl2.v"
86add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl3.v"
87add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl4.v"
88add_file -verilog "../trunk/T1-FPU/fpu_denorm_3b.v"
89add_file -verilog "../trunk/T1-FPU/fpu_denorm_3to1.v"
90add_file -verilog "../trunk/T1-FPU/fpu_denorm_frac.v"
91add_file -verilog "../trunk/T1-FPU/fpu_div.v"
92add_file -verilog "../trunk/T1-FPU/fpu_div_ctl.v"
93add_file -verilog "../trunk/T1-FPU/fpu_div_exp_dp.v"
94add_file -verilog "../trunk/T1-FPU/fpu_div_frac_dp.v"
95add_file -verilog "../trunk/T1-FPU/fpu_in.v"
96add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_2b.v"
97add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_3b.v"
98add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_3to1.v"
99add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_frac.v"
100add_file -verilog "../trunk/T1-FPU/fpu_in_ctl.v"
101add_file -verilog "../trunk/T1-FPU/fpu_in_dp.v"
102add_file -verilog "../trunk/T1-FPU/fpu_mul.v"
103add_file -verilog "../trunk/T1-FPU/fpu_mul_ctl.v"
104add_file -verilog "../trunk/T1-FPU/fpu_mul_exp_dp.v"
105add_file -verilog "../trunk/T1-FPU/fpu_mul_frac_dp.v"
106add_file -verilog "../trunk/T1-FPU/fpu_out.v"
107add_file -verilog "../trunk/T1-FPU/fpu_out_ctl.v"
108add_file -verilog "../trunk/T1-FPU/fpu_out_dp.v"
109add_file -verilog "../trunk/T1-FPU/fpu_rptr_groups.v"
110add_file -verilog "../trunk/T1-FPU/fpu_rptr_macros.v"
111add_file -verilog "../trunk/T1-FPU/fpu_rptr_min_global.v"
112add_file -verilog "../trunk/WB/wb_conbus_arb.v"
113add_file -verilog "../trunk/WB/wb_conbus_defines.v"
114add_file -verilog "../trunk/WB/wb_conbus_top.v"
115add_file -verilog "../trunk/WB2ALTDDR3/dram_wb.v"
116add_file -verilog "../xup5lx110t/cachedir.v"
117add_file -verilog "../xup5lx110t/ipcore_dir/dram_fifo.v"
118add_file -verilog "../xup5lx110t/ipcore_dir/pcx_fifo.v"
119add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/dram.v"
120add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_chipscope.v"
121add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_ctrl.v"
122add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_idelay_ctrl.v"
123add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_infrastructure.v"
124add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_mem_if_top.v"
125add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_calib.v"
126add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_ctl_io.v"
127add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dm_iob.v"
128add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dq_iob.v"
129add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dqs_iob.v"
130add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_init.v"
131add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_init.vhd"
132add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_io.v"
133add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_io.vhd"
134add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_top.v"
135add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_top.vhd"
136add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_write.v"
137add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_write.vhd"
138add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_top.v"
139add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_addr_fifo.v"
140add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_rd.v"
141add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_top.v"
142add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_wr.v"
143add_file -verilog "../trunk/T1-CPU/exu/sparc_exu.v"
144add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alu.v"
145add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alu_16eql.v"
146add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluadder64.v"
147add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluaddsub.v"
148add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alulogic.v"
149add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluor32.v"
150add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluspr.v"
151add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluzcmp64.v"
152add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_byp.v"
153add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_byp_eccgen.v"
154add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div.v"
155add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div_32eql.v"
156add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div_yreg.v"
157add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecc.v"
158add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecc_dec.v"
159add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl.v"
160add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_cnt6.v"
161add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_divcntl.v"
162add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_eccctl.v"
163add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_mdqctl.v"
164add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_wb.v"
165add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclbyplog.v"
166add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclbyplog_rs1.v"
167add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclccr.v"
168add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclcomp7.v"
169add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_reg.v"
170add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml.v"
171add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml_cwp.v"
172add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml_inc3.v"
173add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rndrob.v"
174add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_shft.v"
175add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu.v"
176add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_ctl.v"
177add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_ctl_visctl.v"
178add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_dp.v"
179add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_part_add32.v"
180add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_vis.v"
181add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu.v"
182add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_cmp35.v"
183add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ctr5.v"
184add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_dcl.v"
185add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_dec.v"
186add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_errctl.v"
187add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_errdp.v"
188add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_fcl.v"
189add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_fdp.v"
190add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ifqctl.v"
191add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ifqdp.v"
192add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_imd.v"
193add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_incr46.v"
194add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_invctl.v"
195add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_lfsr5.v"
196add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_lru4.v"
197add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_mbist.v"
198add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_milfsm.v"
199add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par16.v"
200add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par32.v"
201add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par34.v"
202add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_rndrob.v"
203add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_sscan.v"
204add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_swl.v"
205add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_swpla.v"
206add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_thrcmpl.v"
207add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_thrfsm.v"
208add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_wseldp.v"
209add_file -verilog "../trunk/T1-CPU/lsu/lsu.v"
210add_file -verilog "../trunk/T1-CPU/lsu/lsu_asi_decode.v"
211add_file -verilog "../trunk/T1-CPU/lsu/lsu_dc_parity_gen.v"
212add_file -verilog "../trunk/T1-CPU/lsu/lsu_dcache_lfsr.v"
213add_file -verilog "../trunk/T1-CPU/lsu/lsu_dcdp.v"
214add_file -verilog "../trunk/T1-CPU/lsu/lsu_dctl.v"
215add_file -verilog "../trunk/T1-CPU/lsu/lsu_dctldp.v"
216add_file -verilog "../trunk/T1-CPU/lsu/lsu_excpctl.v"
217add_file -verilog "../trunk/T1-CPU/lsu/lsu_pcx_qmon.v"
218add_file -verilog "../trunk/T1-CPU/lsu/lsu_qctl1.v"
219add_file -verilog "../trunk/T1-CPU/lsu/lsu_qctl2.v"
220add_file -verilog "../trunk/T1-CPU/lsu/lsu_qdp1.v"
221add_file -verilog "../trunk/T1-CPU/lsu/lsu_qdp2.v"
222add_file -verilog "../trunk/T1-CPU/lsu/lsu_rrobin_picker2.v"
223add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_ctl.v"
224add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_ctldp.v"
225add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_rwctl.v"
226add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_rwdp.v"
227add_file -verilog "../trunk/T1-CPU/lsu/lsu_tagdp.v"
228add_file -verilog "../trunk/T1-CPU/lsu/lsu_tlbdp.v"
229add_file -verilog "../trunk/T1-CPU/mul/mul64.v"
230add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_cntl.v"
231add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_dp.v"
232add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_top.v"
233add_file -verilog "../trunk/T1-CPU/rtl/bw_clk_cl_sparc_cmp.v"
234add_file -verilog "../trunk/T1-CPU/rtl/cpx_spc_buf.v"
235add_file -verilog "../trunk/T1-CPU/rtl/cpx_spc_rpt.v"
236add_file -verilog "../trunk/T1-CPU/rtl/sparc.v"
237add_file -verilog "../trunk/T1-CPU/rtl/spc_pcx_buf.v"
238add_file -verilog "../trunk/T1-CPU/spu/spu.v"
239add_file -verilog "../trunk/T1-CPU/spu/spu_ctl.v"
240add_file -verilog "../trunk/T1-CPU/spu/spu_lsurpt.v"
241add_file -verilog "../trunk/T1-CPU/spu/spu_lsurpt1.v"
242add_file -verilog "../trunk/T1-CPU/spu/spu_maaddr.v"
243add_file -verilog "../trunk/T1-CPU/spu/spu_maaeqb.v"
244add_file -verilog "../trunk/T1-CPU/spu/spu_mactl.v"
245add_file -verilog "../trunk/T1-CPU/spu/spu_madp.v"
246add_file -verilog "../trunk/T1-CPU/spu/spu_maexp.v"
247add_file -verilog "../trunk/T1-CPU/spu/spu_mald.v"
248add_file -verilog "../trunk/T1-CPU/spu/spu_mamul.v"
249add_file -verilog "../trunk/T1-CPU/spu/spu_mared.v"
250add_file -verilog "../trunk/T1-CPU/spu/spu_mast.v"
251add_file -verilog "../trunk/T1-CPU/spu/spu_wen.v"
252add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_dec64.v"
253add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_intctl.v"
254add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_intdp.v"
255add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_penc64.v"
256add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_zcmp64.v"
257add_file -verilog "../trunk/T1-CPU/tlu/tlu.v"
258add_file -verilog "../trunk/T1-CPU/tlu/tlu_addern_32.v"
259add_file -verilog "../trunk/T1-CPU/tlu/tlu_hyperv.v"
260add_file -verilog "../trunk/T1-CPU/tlu/tlu_incr64.v"
261add_file -verilog "../trunk/T1-CPU/tlu/tlu_misctl.v"
262add_file -verilog "../trunk/T1-CPU/tlu/tlu_mmu_ctl.v"
263add_file -verilog "../trunk/T1-CPU/tlu/tlu_mmu_dp.v"
264add_file -verilog "../trunk/T1-CPU/tlu/tlu_pib.v"
265add_file -verilog "../trunk/T1-CPU/tlu/tlu_prencoder16.v"
266add_file -verilog "../trunk/T1-CPU/tlu/tlu_rrobin_picker.v"
267add_file -verilog "../trunk/T1-CPU/tlu/tlu_tcl.v"
268add_file -verilog "../trunk/T1-CPU/tlu/tlu_tdp.v"
269add_file -verilog "../xup5lx110t/ipcore_dir/pll.v"
270
271
272#implementation: "rev_1"
273impl -add rev_1 -type fpga
274
275#
276#implementation attributes
277
278set_option -vlog_std v2001
279set_option -project_relative_includes 1
280set_option -enable_nfilter 0
281set_option -hdl_define -set "FPGA FPGA_SYN"
282set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/
283
284#device options
285set_option -technology Virtex5
286set_option -part XC5VLX20T
287set_option -package FF323
288set_option -speed_grade -1
289set_option -part_companion ""
290
291#compilation/mapping options
292set_option -use_fsm_explorer 0
293set_option -top_module "W1"
294
295# mapper_options
296set_option -frequency auto
297set_option -write_verilog 0
298set_option -write_vhdl 0
299
300# Xilinx Virtex2
301set_option -run_prop_extract 1
302set_option -maxfan 10000
303set_option -disable_io_insertion 0
304set_option -pipe 1
305set_option -update_models_cp 0
306set_option -retiming 0
307set_option -no_sequential_opt 0
308set_option -fixgatedclocks 3
309set_option -fixgeneratedclocks 3
310
311# Xilinx Virtex5
312set_option -enable_prepacking 1
313
314# NFilter
315set_option -popfeed 0
316set_option -constprop 0
317set_option -createhierarchy 0
318
319# sequential_optimization_options
320set_option -symbolic_fsm_compiler 1
321
322# Compiler Options
323set_option -compiler_compatible 0
324set_option -resource_sharing 1
325
326#VIF options
327set_option -write_vif 1
328
329#automatic place and route (vendor) options
330set_option -write_apr_constraint 1
331
332#set result format/file last
333project -result_file "./rev_1/W1.edf"
334
335#design plan options
336set_option -nfilter_user_path ""
337impl -active "rev_1"
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