| Revision 10,
511 bytes
checked in by pntsvt00, 13 years ago
(diff) |
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versione sintetizzabile
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| 1 | # |
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| 2 | # Constraints generated by Synplify Pro maprc, Build 312R |
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| 3 | # |
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| 4 | |
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| 5 | # Period Constraints |
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| 6 | |
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| 7 | #Begin clock constraints |
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| 8 | NET "clk_in" TNM_NET = "clk_in"; |
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| 9 | TIMESPEC "TS_clk_in" = PERIOD "clk_in" 10.705 ns HIGH 50.00%; |
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| 10 | #End clock constraints |
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| 11 | |
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| 12 | |
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| 13 | |
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| 14 | # I/O Registers Packing Constraints |
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| 15 | INST "flash/wb_dat[*]" IOB=FALSE; # flash/wb_dat[63:0] |
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| 16 | INST "flash/wb1_dat[*]" IOB=FALSE; # flash/wb1_dat[63:0] |
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| 17 | |
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| 18 | # I/O Registers Packing Constraints |
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| 19 | INST "uart16550/regs/i_uart_sync_flops/flop_0[0]" IOB=FALSE; |
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| 20 | |
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| 21 | # End of generated constraints |
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