Changeset 2 in HDLQ


Ignore:
Timestamp:
04/06/11 20:11:32 (13 years ago)
Author:
ttvmrc00
Message:
 
File:
1 edited

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  • Library/MajorityVoter.v

    r1 r2  
    1313        assign out = (fault0) ?  wi3: wi2; 
    1414endmodule 
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