Changeset 26 in XOpenSparcT1 for trunk/os2wb
- Timestamp:
- 04/04/11 11:58:11 (14 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/os2wb/os2wb.v
r23 r26 24 24 25 25 // Core interface 26 input [ 4:0] pcx_req, 26 input [ 4:0] pcx_req, 27 27 input pcx_atom, 28 input [123:0] pcx_data, 28 input [123:0] pcx_data, 29 29 30 output reg [ 4:0] pcx_grant, 30 31 output reg cpx_ready, … … 235 236 `TEST_DRAM_1: 236 237 begin 237 $display("INFO: OS2WB: TEST_DRAM_1");238 //$display("INFO: OS2WB: TEST_DRAM_1"); 238 239 wb_cycle<=1; 239 240 wb_strobe<=1; … … 245 246 if(wb_ack) 246 247 begin 247 $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);248 //$display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); 248 249 wb_strobe<=0; 249 250 if(wb_addr<`MEM_SIZE-8) … … 265 266 `TEST_DRAM_3: 266 267 begin 267 $display("INFO: OS2WB: TEST_DRAM_3");268 //$display("INFO: OS2WB: TEST_DRAM_3"); 268 269 wb_cycle<=1; 269 270 wb_strobe<=1; … … 274 275 if(wb_ack) 275 276 begin 276 $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time);277 // $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); 277 278 wb_strobe<=0; 278 279 if(wb_addr<`MEM_SIZE-8) … … 284 285 // end 285 286 //else 286 // $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); 287 $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); 287 // $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); 288 288 end 289 289 else 290 290 begin 291 $display("INFO: OS2WB: INIT_DRAM at %t",$time);291 //$display("INFO: OS2WB: INIT_DRAM at %t",$time); 292 292 state<=`INIT_DRAM_1; 293 293 wb_cycle<=0; … … 323 323 else 324 324 begin 325 $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time);325 //$display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); 326 326 state<=`WAKEUP; 327 327 wb_cycle<=0; … … 393 393 `PCX_REQ_2ND: 394 394 begin 395 $display("INFO: OS2WB: GOT_PCX_REQ_2ND"); 395 396 pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics 396 397 if(`DEBUGGING) … … 407 408 if(pcx_packet_d[111]==1'b1) // Invalidate request 408 409 begin 410 $display("INFO: OS2WB: INVALIDATE"); 409 411 cpx_packet_1[144]<=1; // Valid 410 412 cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK … … 423 425 if(pcx_packet_d[122:118]!=5'b01001) // Not INT 424 426 begin 427 $display("INFO: OS2WB: PCX_REQ_STEP1"); 425 428 wb_cycle<=1'b1; 426 429 wb_strobe<=1'b1; 427 430 if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) || pcx_packet_d[122:118]==5'b00010 || pcx_packet_d[122:118]==5'b00100 || pcx_packet_d[122:118]==5'b00110) 431 begin 432 $display("INFO: OS2WB: load/streadload ecc"); 428 433 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first 429 else 434 end 435 else 430 436 if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4]) 437 begin 438 $display("INFO: OS2WB: ifill"); 431 439 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill 432 else 440 end 441 else 433 442 if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8 434 443 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000}; … … 446 455 5'b00000://Load 447 456 begin 457 $display("INFO: OS2WB: PCX_REQ_STEP1, Load"); 448 458 wb_we<=0; 449 459 if(!pcx_packet_d[110] && !pcx_packet_d[117]) … … 492 502 5'b00001://Store 493 503 begin 504 $display("INFO: OS2WB: PCX_REQ_STEP1, Store"); 494 505 wb_we<=1; 495 506 case({icache_hit,dcache0_hit}) … … 538 549 5'b00010://CAS 539 550 begin 551 $display("INFO: OS2WB: PCX_REQ_STEP1, CAS"); 540 552 wb_we<=0; //Load first 541 553 case({icache_hit,dcache0_hit}) … … 555 567 5'b00100://STRLOAD 556 568 begin 569 $display("INFO: OS2WB: PCX_REQ_STEP1, STRLOAD"); 557 570 wb_we<=0; 558 571 wb_sel<=8'b11111111; // Stream loads are always 128 bit … … 560 573 5'b00101://STRSTORE 561 574 begin 575 $display("INFO: OS2WB: PCX_REQ_STEP1, STRSTORE"); 562 576 wb_we<=1; 563 577 case({icache_hit,dcache0_hit}) … … 606 620 5'b00110://SWAP/LDSTUB 607 621 begin 622 $display("INFO: OS2WB: PCX_REQ_STEP1, SWAP/LDSTUB"); 608 623 case({icache_hit,dcache0_hit}) 609 624 8'b00000000:; … … 622 637 end 623 638 5'b01001://INT 624 if(pcx_packet_d[117]) // Flush 639 begin 640 $display("INFO: OS2WB: PCX_REQ_STEP1, INT"); 641 if(pcx_packet_d[117]) // Flush 625 642 cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer 626 643 else // Tread-to-thread interrupt 627 644 cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]}; 628 //5'b01010: FP1 - processed by separate state 629 //5'b01011: FP2 - processed by separate state 630 //5'b01101: FWDREQ - not implemented 631 //5'b01110: FWDREPL - not implemented 632 5'b10000://IFILL 633 begin 645 //5'b01010: FP1 - processed by separate state 646 //5'b01011: FP2 - processed by separate state 647 //5'b01101: FWDREQ - not implemented 648 //5'b01110: FWDREPL - not implemented 649 end 650 5'b10000://IFILL 651 begin 652 $display("INFO: OS2WB: PCX_REQ_STEP1, IFILL"); 634 653 wb_we<=0; 635 654 if(!pcx_req_d[4]) // not I/O access … … 668 687 if(wb_ack) 669 688 begin 689 $display("INFO: OS2WB: PCX_REQ_STEP1_1 wb_addr = %x",wb_addr); 670 690 cpx_packet_1[144]<=1; // Valid 671 cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; 691 cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill 672 692 cpx_packet_1[138:137]<=0; // Error 673 693 cpx_packet_1[136]<=pcx_packet_d[117] || (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too … … 821 841 5'b10000://IFILL 822 842 begin 843 $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, wb_addr = %x wb_data_i= %x",wb_addr, wb_data_i); 844 $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, cpx_packet_1 = %x %x",wb_data_i,wb_data_i); 823 845 cpx_packet_1[143:140]<=4'b0001; // Type 824 846 cpx_packet_2[143:140]<=4'b0001; // Type … … 1073 1095 `CPX_READY_1: 1074 1096 begin 1097 $display("INFO: OS2WB: CPX_READY_1"); 1075 1098 cpx_ready<=1; 1076 1099 cpx_packet<=cpx_packet_1; … … 1087 1110 `CPX_READY_2: 1088 1111 begin 1112 $display("INFO: OS2WB: CPX_READY_2"); 1089 1113 cpx_ready<=1; 1090 1114 cpx_packet<=cpx_packet_2; … … 1093 1117 `PCX_UNKNOWN: 1094 1118 begin 1119 $display("INFO: OS2WB: PCX_UNKNOWN"); 1095 1120 wb_sel<=8'b10100101; // Illegal eye-catching value for debugging 1096 1121 state<=`PCX_IDLE; … … 1250 1275 .enable(dir_en), 1251 1276 .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init), 1252 .address_a({2'b0 ,icache_index}),1277 .address_a({2'b00,icache_index}), 1253 1278 .data_a(icache_data), 1254 1279 .q_a(icache0_do), 1255 1280 1256 1281 .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), 1257 .address_b({2'b0 ,icache_index}),1282 .address_b({2'b01,icache_index}), 1258 1283 .data_b(icache_data), 1259 1284 .q_b(icache1_do) … … 1264 1289 .enable(dir_en), 1265 1290 .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init), 1266 .address_a({2'b0 ,icache_index}),1291 .address_a({2'b00,icache_index}), 1267 1292 .data_a(icache_data), 1268 1293 .q_a(icache2_do), 1269 1294 1270 1295 .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init), 1271 .address_b({2'b0 ,icache_index}),1296 .address_b({2'b01,icache_index}), 1272 1297 .data_b(icache_data), 1273 1298 .q_b(icache3_do)
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