Changeset 26 in XOpenSparcT1
- Timestamp:
- 04/04/11 11:58:11 (14 years ago)
- Location:
- trunk
- Files:
-
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/T1-CPU/exu/sparc_exu.v
r6 r26 595 595 assign syndrome[3]=ifu_exu_ren3_s_d && (irf_byp_rs3h_data_d_l_ref!=irf_byp_rs3h_data_d_l_fpga); 596 596 597 assign ILA_DATA[1:0]=ifu_exu_tid_s2;598 assign ILA_DATA[6:2]=ifu_exu_rs1_s;599 assign ILA_DATA[11:7]=ifu_exu_rs2_s;600 assign ILA_DATA[16:12]=ifu_exu_rs3_s;601 assign ILA_DATA[17]=ifu_exu_ren1_s;602 assign ILA_DATA[18]=ifu_exu_ren2_s;603 assign ILA_DATA[19]=ifu_exu_ren3_s;604 assign ILA_DATA[20]=ecl_irf_wen_w;605 assign ILA_DATA[21]=ecl_irf_wen_w2;606 assign ILA_DATA[26:22]=ecl_irf_rd_m_d;607 assign ILA_DATA[31:27]=ecl_irf_rd_g_d;608 assign ILA_DATA[103:32]=byp_irf_rd_data_w;609 assign ILA_DATA[175:104]=byp_irf_rd_data_w2;610 assign ILA_DATA[177:176]=ecl_irf_tid_m;611 assign ILA_DATA[179:178]=ecl_irf_tid_g;612 assign ILA_DATA[182:180]=rml_irf_old_lo_cwp_e;613 assign ILA_DATA[185:183]=rml_irf_new_lo_cwp_e;614 assign ILA_DATA[187:186]=rml_irf_old_e_cwp_e;615 assign ILA_DATA[189:188]=rml_irf_new_e_cwp_e;616 assign ILA_DATA[190]=rml_irf_swap_even_e;617 assign ILA_DATA[191]=rml_irf_swap_odd_e;618 assign ILA_DATA[192]=rml_irf_swap_local_e;619 assign ILA_DATA[193]=rml_irf_kill_restore_w;620 assign ILA_DATA[195:194]=rml_irf_cwpswap_tid_e;621 assign ILA_DATA[197:196]=rml_irf_old_agp;622 assign ILA_DATA[199:198]=rml_irf_new_agp;623 assign ILA_DATA[200]=rml_irf_swap_global;624 assign ILA_DATA[202:201]=rml_irf_global_tid;625 assign ILA_DATA[274:203]=irf_byp_rs1_data_d_l_ref;626 assign ILA_DATA[346:275]=irf_byp_rs2_data_d_l_ref;627 assign ILA_DATA[418:347]=irf_byp_rs3_data_d_l_ref;628 assign ILA_DATA[450:419]=irf_byp_rs3h_data_d_l_ref;629 assign ILA_DATA[522:451]=irf_byp_rs1_data_d_l_fpga;630 assign ILA_DATA[594:523]=irf_byp_rs2_data_d_l_fpga;631 assign ILA_DATA[666:595]=irf_byp_rs3_data_d_l_fpga;632 assign ILA_DATA[698:667]=irf_byp_rs3h_data_d_l_fpga;633 assign ILA_DATA[702:699]=syndrome;// && read_known0;634 assign ILA_DATA[705:703]=current_cwp[2:0];635 assign ILA_DATA[706]=0;636 assign ILA_DATA[737:707]={cnt[14:0],err_cnt};637 assign ILA_DATA[738]=rml_irf_swap_local_e && (current_window!=rml_irf_old_lo_cwp_e);597 //assign ILA_DATA[1:0]=ifu_exu_tid_s2; 598 //assign ILA_DATA[6:2]=ifu_exu_rs1_s; 599 //assign ILA_DATA[11:7]=ifu_exu_rs2_s; 600 //assign ILA_DATA[16:12]=ifu_exu_rs3_s; 601 //assign ILA_DATA[17]=ifu_exu_ren1_s; 602 //assign ILA_DATA[18]=ifu_exu_ren2_s; 603 //assign ILA_DATA[19]=ifu_exu_ren3_s; 604 //assign ILA_DATA[20]=ecl_irf_wen_w; 605 //assign ILA_DATA[21]=ecl_irf_wen_w2; 606 //assign ILA_DATA[26:22]=ecl_irf_rd_m_d; 607 //assign ILA_DATA[31:27]=ecl_irf_rd_g_d; 608 //assign ILA_DATA[103:32]=byp_irf_rd_data_w; 609 //assign ILA_DATA[175:104]=byp_irf_rd_data_w2; 610 //assign ILA_DATA[177:176]=ecl_irf_tid_m; 611 //assign ILA_DATA[179:178]=ecl_irf_tid_g; 612 //assign ILA_DATA[182:180]=rml_irf_old_lo_cwp_e; 613 //assign ILA_DATA[185:183]=rml_irf_new_lo_cwp_e; 614 //assign ILA_DATA[187:186]=rml_irf_old_e_cwp_e; 615 //assign ILA_DATA[189:188]=rml_irf_new_e_cwp_e; 616 //assign ILA_DATA[190]=rml_irf_swap_even_e; 617 //assign ILA_DATA[191]=rml_irf_swap_odd_e; 618 //assign ILA_DATA[192]=rml_irf_swap_local_e; 619 //assign ILA_DATA[193]=rml_irf_kill_restore_w; 620 //assign ILA_DATA[195:194]=rml_irf_cwpswap_tid_e; 621 //assign ILA_DATA[197:196]=rml_irf_old_agp; 622 //assign ILA_DATA[199:198]=rml_irf_new_agp; 623 //assign ILA_DATA[200]=rml_irf_swap_global; 624 //assign ILA_DATA[202:201]=rml_irf_global_tid; 625 //assign ILA_DATA[274:203]=irf_byp_rs1_data_d_l_ref; 626 //assign ILA_DATA[346:275]=irf_byp_rs2_data_d_l_ref; 627 //assign ILA_DATA[418:347]=irf_byp_rs3_data_d_l_ref; 628 //assign ILA_DATA[450:419]=irf_byp_rs3h_data_d_l_ref; 629 //assign ILA_DATA[522:451]=irf_byp_rs1_data_d_l_fpga; 630 //assign ILA_DATA[594:523]=irf_byp_rs2_data_d_l_fpga; 631 //assign ILA_DATA[666:595]=irf_byp_rs3_data_d_l_fpga; 632 //assign ILA_DATA[698:667]=irf_byp_rs3h_data_d_l_fpga; 633 //assign ILA_DATA[702:699]=syndrome;// && read_known0; 634 //assign ILA_DATA[705:703]=current_cwp[2:0]; 635 //assign ILA_DATA[706]=0; 636 //assign ILA_DATA[737:707]={cnt[14:0],err_cnt}; 637 //assign ILA_DATA[738]=rml_irf_swap_local_e && (current_window!=rml_irf_old_lo_cwp_e); 638 638 //assign ILA_DATA[699]=(irf_byp_rs1_data_d_l_fpga!=irf_byp_rs1_data_d_l_fpga_d) && (irf_byp_rs1_data_d_l==irf_byp_rs1_data_d_l_d); 639 639 //assign ILA_DATA[700]=(irf_byp_rs2_data_d_l_fpga!=irf_byp_rs2_data_d_l_fpga_d) && (irf_byp_rs2_data_d_l==irf_byp_rs2_data_d_l_d); … … 645 645 bw_r_irf_fpga1 irf( 646 646 647 .current_cwp(current_cwp ),647 .current_cwp(current_cwp[11:0]), 648 648 .so (short_scan0_1), 649 649 .si (short_si0), -
trunk/T1-CPU/exu/sparc_exu_alu.v
r6 r26 106 106 107 107 // Zero comparison for exu_ifu_regz_e 108 sparc_exu_aluzcmp64 regzcmp(.in(byp_alu_rcc_data_e[63:0]), .zero64(exu_ifu_regz_e) );108 sparc_exu_aluzcmp64 regzcmp(.in(byp_alu_rcc_data_e[63:0]), .zero64(exu_ifu_regz_e),.zero32()); 109 109 assign exu_ifu_regn_e = byp_alu_rcc_data_e[63]; 110 110 -
trunk/T1-common/srams/bw_r_irf.v
r22 r26 1362 1362 new_agp_d2[1:0] <= new_agp_d1[1:0]; 1363 1363 end 1364 /* 1364 1365 // synthesis traslate off 1366 `ifdef DEBUG 1367 1365 1368 always @(posedge clk) begin 1366 1369 if (wr_en) begin … … 1385 1388 end 1386 1389 end 1387 */ 1390 1391 // synthesis traslate on 1392 `endif 1393 1388 1394 endmodule 1389 1395 -
trunk/WB/wb_conbus_top.v
r22 r26 137 137 parameter s0_addr = 1'b0; // slave 0 address 138 138 139 //address for a 32MB flash from 0x800000ff_f0800000 to 0x800000ff_f0ffffff 139 //PCX request on 800000ff_f0000020 140 //address for a 32MB flash from 0x800000ff_f0000000 to 0x800000ff_f07fffff 140 141 //Check address_w 141 142 // 32 MB --> 8 MW X32 bits --> 2^23 --> addr_w=64-23=41 -
trunk/Xilinx/cachedir.v
r17 r26 37 37 always @(posedge clock) 38 38 begin 39 39 if (enable) 40 40 if (wren_a) 41 41 mem1[address_a] <= data_a; … … 46 46 always @(posedge clock) 47 47 begin 48 48 if (enable) 49 49 if (wren_b) 50 50 mem2[address_b] <= data_b; -
trunk/os2wb/os2wb.v
r23 r26 24 24 25 25 // Core interface 26 input [ 4:0] pcx_req, 26 input [ 4:0] pcx_req, 27 27 input pcx_atom, 28 input [123:0] pcx_data, 28 input [123:0] pcx_data, 29 29 30 output reg [ 4:0] pcx_grant, 30 31 output reg cpx_ready, … … 235 236 `TEST_DRAM_1: 236 237 begin 237 $display("INFO: OS2WB: TEST_DRAM_1");238 //$display("INFO: OS2WB: TEST_DRAM_1"); 238 239 wb_cycle<=1; 239 240 wb_strobe<=1; … … 245 246 if(wb_ack) 246 247 begin 247 $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);248 //$display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); 248 249 wb_strobe<=0; 249 250 if(wb_addr<`MEM_SIZE-8) … … 265 266 `TEST_DRAM_3: 266 267 begin 267 $display("INFO: OS2WB: TEST_DRAM_3");268 //$display("INFO: OS2WB: TEST_DRAM_3"); 268 269 wb_cycle<=1; 269 270 wb_strobe<=1; … … 274 275 if(wb_ack) 275 276 begin 276 $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time);277 // $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); 277 278 wb_strobe<=0; 278 279 if(wb_addr<`MEM_SIZE-8) … … 284 285 // end 285 286 //else 286 // $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); 287 $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); 287 // $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); 288 288 end 289 289 else 290 290 begin 291 $display("INFO: OS2WB: INIT_DRAM at %t",$time);291 //$display("INFO: OS2WB: INIT_DRAM at %t",$time); 292 292 state<=`INIT_DRAM_1; 293 293 wb_cycle<=0; … … 323 323 else 324 324 begin 325 $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time);325 //$display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); 326 326 state<=`WAKEUP; 327 327 wb_cycle<=0; … … 393 393 `PCX_REQ_2ND: 394 394 begin 395 $display("INFO: OS2WB: GOT_PCX_REQ_2ND"); 395 396 pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics 396 397 if(`DEBUGGING) … … 407 408 if(pcx_packet_d[111]==1'b1) // Invalidate request 408 409 begin 410 $display("INFO: OS2WB: INVALIDATE"); 409 411 cpx_packet_1[144]<=1; // Valid 410 412 cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK … … 423 425 if(pcx_packet_d[122:118]!=5'b01001) // Not INT 424 426 begin 427 $display("INFO: OS2WB: PCX_REQ_STEP1"); 425 428 wb_cycle<=1'b1; 426 429 wb_strobe<=1'b1; 427 430 if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) || pcx_packet_d[122:118]==5'b00010 || pcx_packet_d[122:118]==5'b00100 || pcx_packet_d[122:118]==5'b00110) 431 begin 432 $display("INFO: OS2WB: load/streadload ecc"); 428 433 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first 429 else 434 end 435 else 430 436 if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4]) 437 begin 438 $display("INFO: OS2WB: ifill"); 431 439 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill 432 else 440 end 441 else 433 442 if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8 434 443 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000}; … … 446 455 5'b00000://Load 447 456 begin 457 $display("INFO: OS2WB: PCX_REQ_STEP1, Load"); 448 458 wb_we<=0; 449 459 if(!pcx_packet_d[110] && !pcx_packet_d[117]) … … 492 502 5'b00001://Store 493 503 begin 504 $display("INFO: OS2WB: PCX_REQ_STEP1, Store"); 494 505 wb_we<=1; 495 506 case({icache_hit,dcache0_hit}) … … 538 549 5'b00010://CAS 539 550 begin 551 $display("INFO: OS2WB: PCX_REQ_STEP1, CAS"); 540 552 wb_we<=0; //Load first 541 553 case({icache_hit,dcache0_hit}) … … 555 567 5'b00100://STRLOAD 556 568 begin 569 $display("INFO: OS2WB: PCX_REQ_STEP1, STRLOAD"); 557 570 wb_we<=0; 558 571 wb_sel<=8'b11111111; // Stream loads are always 128 bit … … 560 573 5'b00101://STRSTORE 561 574 begin 575 $display("INFO: OS2WB: PCX_REQ_STEP1, STRSTORE"); 562 576 wb_we<=1; 563 577 case({icache_hit,dcache0_hit}) … … 606 620 5'b00110://SWAP/LDSTUB 607 621 begin 622 $display("INFO: OS2WB: PCX_REQ_STEP1, SWAP/LDSTUB"); 608 623 case({icache_hit,dcache0_hit}) 609 624 8'b00000000:; … … 622 637 end 623 638 5'b01001://INT 624 if(pcx_packet_d[117]) // Flush 639 begin 640 $display("INFO: OS2WB: PCX_REQ_STEP1, INT"); 641 if(pcx_packet_d[117]) // Flush 625 642 cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer 626 643 else // Tread-to-thread interrupt 627 644 cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]}; 628 //5'b01010: FP1 - processed by separate state 629 //5'b01011: FP2 - processed by separate state 630 //5'b01101: FWDREQ - not implemented 631 //5'b01110: FWDREPL - not implemented 632 5'b10000://IFILL 633 begin 645 //5'b01010: FP1 - processed by separate state 646 //5'b01011: FP2 - processed by separate state 647 //5'b01101: FWDREQ - not implemented 648 //5'b01110: FWDREPL - not implemented 649 end 650 5'b10000://IFILL 651 begin 652 $display("INFO: OS2WB: PCX_REQ_STEP1, IFILL"); 634 653 wb_we<=0; 635 654 if(!pcx_req_d[4]) // not I/O access … … 668 687 if(wb_ack) 669 688 begin 689 $display("INFO: OS2WB: PCX_REQ_STEP1_1 wb_addr = %x",wb_addr); 670 690 cpx_packet_1[144]<=1; // Valid 671 cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; 691 cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill 672 692 cpx_packet_1[138:137]<=0; // Error 673 693 cpx_packet_1[136]<=pcx_packet_d[117] || (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too … … 821 841 5'b10000://IFILL 822 842 begin 843 $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, wb_addr = %x wb_data_i= %x",wb_addr, wb_data_i); 844 $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, cpx_packet_1 = %x %x",wb_data_i,wb_data_i); 823 845 cpx_packet_1[143:140]<=4'b0001; // Type 824 846 cpx_packet_2[143:140]<=4'b0001; // Type … … 1073 1095 `CPX_READY_1: 1074 1096 begin 1097 $display("INFO: OS2WB: CPX_READY_1"); 1075 1098 cpx_ready<=1; 1076 1099 cpx_packet<=cpx_packet_1; … … 1087 1110 `CPX_READY_2: 1088 1111 begin 1112 $display("INFO: OS2WB: CPX_READY_2"); 1089 1113 cpx_ready<=1; 1090 1114 cpx_packet<=cpx_packet_2; … … 1093 1117 `PCX_UNKNOWN: 1094 1118 begin 1119 $display("INFO: OS2WB: PCX_UNKNOWN"); 1095 1120 wb_sel<=8'b10100101; // Illegal eye-catching value for debugging 1096 1121 state<=`PCX_IDLE; … … 1250 1275 .enable(dir_en), 1251 1276 .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init), 1252 .address_a({2'b0 ,icache_index}),1277 .address_a({2'b00,icache_index}), 1253 1278 .data_a(icache_data), 1254 1279 .q_a(icache0_do), 1255 1280 1256 1281 .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), 1257 .address_b({2'b0 ,icache_index}),1282 .address_b({2'b01,icache_index}), 1258 1283 .data_b(icache_data), 1259 1284 .q_b(icache1_do) … … 1264 1289 .enable(dir_en), 1265 1290 .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init), 1266 .address_a({2'b0 ,icache_index}),1291 .address_a({2'b00,icache_index}), 1267 1292 .data_a(icache_data), 1268 1293 .q_a(icache2_do), 1269 1294 1270 1295 .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init), 1271 .address_b({2'b0 ,icache_index}),1296 .address_b({2'b01,icache_index}), 1272 1297 .data_b(icache_data), 1273 1298 .q_b(icache3_do) -
trunk/sim/flash.v
r21 r26 42 42 $readmemh(memfilename, mem); 43 43 $display("INFO: MEMH %m: Memory initialization completed"); 44 //for(i=0; i<=1023; i=i+1) $display("mem_i = %x",mem[i]) ; 44 45 end 45 46 `endif 46 47 47 48 assign flash_data = !flash_oen ? data :16'hzzzz; 48 49 49 50 50 always @(posedge flash_clk) begin 51 51 // Read cycle 52 52 if (!flash_oen & flash_wen) 53 data <= mem[flash_addr]; 53 begin 54 //$display("INFO: flash: read from address %x data %x",flash_addr, mem[flash_addr]); 55 data <= mem[flash_addr]; 56 end 54 57 else // Write cycle 55 if (flash_oen & !flash_wen) mem[flash_addr] <= flash_data; 56 end 58 if (flash_oen & !flash_wen) 59 $display("INFO: flash: write to address %x data %x (now disabled)",flash_addr,flash_data); 60 //mem[flash_addr] <= flash_data; FIXME: errouneous spourious writes in flash 61 end 57 62 endmodule 58 63 -
trunk/sim/simula.do
r22 r26 1 1 #start with: vsim -c -do simula.do 2 2 3 set DEFINE +define+DEBUG+FPGA_SYN 4 #+FPGA_NEW_IRF 5 set INCLUDEDIR +incdir+../T1-common/include/ 3 6 vlib work 4 7 … … 7 10 #Compile all modules# 8 11 9 vlog +incdir+../T1-common/include/../T1-common/common/*.v10 vlog +incdir+../T1-common/include/../Top/*.v11 vlog +incdir+../OC-UART +incdir+../T1-common/include/../OC-UART/*.v12 vlog +incdir+../T1-common/include/../NOR-flash/*.v13 vlog +incdir+../T1-common/include/../os2wb/*.v14 vlog +incdir+../T1-common/include/../T1-common/m1/*.V15 vlog +define+FPGA_SYN +incdir+../T1-common/include/../T1-common/srams/*.v16 vlog +incdir+../T1-common/include/../T1-common/u1/*.V17 vlog +incdir+../T1-common/include/ ../T1-FPU/*.v18 vlog +incdir+../T1-common/include/+incdir+../WB ../WB/*.v19 vlog +incdir+../T1-common/include/../WB2ALTDDR3/*.v20 vlog +incdir+../T1-common/include/../Xilinx/*.v21 vlog +incdir+../T1-common/include/../T1-CPU/exu/*.v22 vlog +incdir+../T1-common/include/../T1-CPU/ffu/*.v23 vlog +incdir+../T1-common/include/../T1-CPU/ifu/*.v24 vlog +incdir+../T1-common/include/../T1-CPU/lsu/*.v25 vlog +incdir+../T1-common/include/../T1-CPU/mul/*.v26 vlog +incdir+../T1-common/include/../T1-CPU/rtl/*.v27 vlog +incdir+../T1-common/include/../T1-CPU/spu/*.v28 vlog +incdir+../T1-common/include/../T1-CPU/tlu/*.v12 vlog $DEFINE $INCLUDEDIR ../T1-common/common/*.v 13 vlog $DEFINE $INCLUDEDIR ../Top/*.v 14 vlog $DEFINE +incdir+../OC-UART $INCLUDEDIR ../OC-UART/*.v 15 vlog $DEFINE $INCLUDEDIR ../NOR-flash/*.v 16 vlog $DEFINE $INCLUDEDIR ../os2wb/*.v 17 vlog $DEFINE $INCLUDEDIR ../T1-common/m1/*.V 18 vlog $DEFINE $INCLUDEDIR ../T1-common/srams/*.v 19 vlog $DEFINE $INCLUDEDIR ../T1-common/u1/*.V 20 vlog $DEFINE $INCLUDEDIR/ ../T1-FPU/*.v 21 vlog $DEFINE $INCLUDEDIR +incdir+../WB ../WB/*.v 22 vlog $DEFINE $INCLUDEDIR ../WB2ALTDDR3/*.v 23 vlog $DEFINE $INCLUDEDIR ../Xilinx/*.v 24 vlog $DEFINE $INCLUDEDIR ../T1-CPU/exu/*.v 25 vlog $DEFINE $INCLUDEDIR ../T1-CPU/ffu/*.v 26 vlog $DEFINE $INCLUDEDIR ../T1-CPU/ifu/*.v 27 vlog $DEFINE $INCLUDEDIR ../T1-CPU/lsu/*.v 28 vlog $DEFINE $INCLUDEDIR ../T1-CPU/mul/*.v 29 vlog $DEFINE $INCLUDEDIR ../T1-CPU/rtl/*.v 30 vlog $DEFINE $INCLUDEDIR ../T1-CPU/spu/*.v 31 vlog $DEFINE $INCLUDEDIR ../T1-CPU/tlu/*.v 29 32 30 33 #Compile files in sim folder (excluding model parameter file)# -
trunk/sw/hello.c
r20 r26 2 2 3 3 int main() { 4 asm("mov 0x00, %fp \n"); 4 5 register unsigned long* address; 5 6 address = (unsigned long*)0x0000CAC0; -
trunk/sw/hello.dump
r19 r26 6 6 7 7 0000000000000000 <main>: 8 0: 9d e3 bf 40 save %sp, -192, %sp 9 4: 82 10 23 2b mov 0x32b, %g1 10 8: 83 28 70 06 sllx %g1, 6, %g1 11 c: c2 77 a7 f7 stx %g1, [ %fp + 0x7f7 ] 12 10: c2 5f a7 f7 ldx [ %fp + 0x7f7 ], %g1 13 14: 05 30 68 30 sethi %hi(0xc1a0c000), %g2 14 18: 84 10 a1 a0 or %g2, 0x1a0, %g2 ! c1a0c1a0 <main+0xc1a0c1a0> 15 1c: c4 70 40 00 stx %g2, [ %g1 ] 16 20: 82 10 23 2b mov 0x32b, %g1 17 24: 83 28 70 06 sllx %g1, 6, %g1 18 28: c2 77 a7 f7 stx %g1, [ %fp + 0x7f7 ] 19 2c: c2 5f a7 f7 ldx [ %fp + 0x7f7 ], %g1 20 30: 05 3e ae 84 sethi %hi(0xfaba1000), %g2 21 34: 84 10 a2 10 or %g2, 0x210, %g2 ! faba1210 <main+0xfaba1210> 22 38: c4 70 40 00 stx %g2, [ %g1 ] 23 3c: 82 10 20 00 clr %g1 24 40: 83 38 60 00 sra %g1, 0, %g1 25 44: b0 10 00 01 mov %g1, %i0 26 48: 81 cf e0 08 rett %i7 + 8 27 4c: 01 00 00 00 nop 8 4: bc 10 20 00 clr %fp 9 8: 82 10 23 2b mov 0x32b, %g1 10 c: a1 28 70 06 sllx %g1, 6, %l0 11 10: 03 30 68 30 sethi %hi(0xc1a0c000), %g1 12 14: 82 10 61 a0 or %g1, 0x1a0, %g1 ! c1a0c1a0 <main+0xc1a0c1a0> 13 18: c2 74 00 00 stx %g1, [ %l0 ] 14 1c: 82 10 23 2b mov 0x32b, %g1 15 20: a1 28 70 06 sllx %g1, 6, %l0 16 24: 03 3e ae 84 sethi %hi(0xfaba1000), %g1 17 28: 82 10 62 10 or %g1, 0x210, %g1 ! faba1210 <main+0xfaba1210> 18 2c: c2 74 00 00 stx %g1, [ %l0 ] 19 30: 82 10 20 00 clr %g1 20 34: 83 38 60 00 sra %g1, 0, %g1 21 38: b0 10 00 01 mov %g1, %i0 22 3c: 81 cf e0 08 rett %i7 + 8 23 40: 01 00 00 00 nop -
trunk/tools/dump2hex.php
r25 r26 6 6 7 7 // Discard first lines 8 for($i=0; $i< 7; $i++) fgets($fp);8 for($i=0; $i<8; $i++) fgets($fp); 9 9 10 // instruction start at address 10h 11 //echo "@ 10\n"; 12 echo "// inserisco 16 ff per partire da 10h e scrivo op4,op3,op2,op1 \n"; 13 echo "ffff\n"; 14 echo "ffff\n"; 15 echo "ffff\n"; 16 echo "ffff\n"; 17 echo "ffff\n"; 18 echo "ffff\n"; 19 echo "ffff\n"; 20 echo "ffff\n"; 21 echo "ffff\n"; 22 echo "ffff\n"; 23 echo "ffff\n"; 24 echo "ffff\n"; 25 echo "ffff\n"; 26 echo "ffff\n"; 27 echo "ffff\n"; 28 echo "ffff\n"; 10 29 // Print only the opcodes to stdout 11 30 while (!feof($fp)) { 12 31 $line = fgets($fp); 13 /*$opcode = substr($line, 8, 8); 14 $caratteri = strlen($opcode); 32 $opcode1 = substr($line, 6, 2); 33 $opcode2 = substr($line, 9, 2); 34 $opcode3 = substr($line, 12, 2); 35 $opcode4 = substr($line, 15, 2); 36 $caratteri = strlen($opcode1); 15 37 if($caratteri != 0){ 16 echo $opcode."\n"; 17 }*/ 18 19 $opcode = substr($line, 6, 2); 20 $opcode2 = substr($line, 9, 2); 21 $caratteri = strlen($opcode); 22 if($caratteri != 0){ 23 echo $opcode.$opcode2; 38 echo $opcode2.$opcode1; 39 //echo $opcode1.$opcode2; 24 40 echo "\t //".$line; 25 $opcode = substr($line, 12, 2); 26 $opcode2 = substr($line, 15, 2); 27 echo $opcode.$opcode2."\n"; 41 echo $opcode4.$opcode3."\n"; 42 //echo $opcode3.$opcode4."\n"; 28 43 } 29 44 else{
Note: See TracChangeset
for help on using the changeset viewer.