Changeset 27 in XOpenSparcT1

Timestamp:

04/05/11 09:58:40 (14 years ago)

Author:

pntsvt00

Message:

eliminato baco store consecutivi. esegue correttamente il codice

Location:

trunk

Files:

• NOR-flash/WBFLASH.v (modified) (2 diffs)
• T1-common/srams/bw_r_scm.v (modified) (1 diff)
• Top/W1.v (modified) (2 diffs)
• Xilinx/cachedir.v (modified) (1 diff)
• os2wb/os2wb.v (modified) (2 diffs)
• sim/simula.do (modified) (1 diff)
• sw/hello2.c (added)

trunk/NOR-flash/WBFLASH.v

@@ -58 +58 @@
 assign wb_err_o=0;
 assign wb_rty_o=0;
+assign wb1_err_o=0;
+assign wb1_rty_o=0;
 
 reg  [1:0] wordcnt;
@@ -70 +72 @@
    if(wb_rst_i)
       begin
+         wb_ack_o<=0;
+         wb1_ack_o<=0;
          cache_addr<=64'b0;
          cache_addr1<=64'b0;

trunk/T1-common/srams/bw_r_scm.v

@@ -294 +294 @@
 
 // tolgo stb_ramc_d dalla sensitivity list...
-always @( byte_overlap or ramc_entry,cam_tag or cam_bmask or ptag_hit or byte_match)
+always @( byte_overlap or ramc_entry,cam_tag or cam_bmask or ptag_hit or byte_match or stb_ramc_d)
   begin
         for (l=0;l<NUMENTRIES;l=l+1)

trunk/Top/W1.v

@@ -304 +304 @@
     .s2_cyc_o(s2_cyc_o), 
     .s2_stb_o(s2_stb_o), 
-    .s2_ack_i(s2_ack_i), 
-    .s2_err_i(s2_err_i), 
-    .s2_rty_i(s2_rty_i), 
+    .s2_ack_i(1'b0), 
+    .s2_err_i(1'b0), 
+    .s2_rty_i(1'b0), 
+    //.s2_ack_i(s2_ack_i), 
+    //.s2_err_i(s2_err_i), 
+    //.s2_rty_i(s2_rty_i), 
     .s2_cab_o(s2_cab_o), 
 
@@ -318 +321 @@
     .s3_stb_o(s3_stb_o), 
     .s3_ack_i(s3_ack_i), 
-    .s3_err_i(s3_err_i), 
-    .s3_rty_i(s3_rty_i), 
-    .s3_cab_o(s3_cab_o), 
+    .s3_err_i(1'b0), 
+    .s3_rty_i(1'b0), 
+    .s3_cab_o(), 
 
     //Second flash interface for fff8xxxxxx ram disk addressing

trunk/Xilinx/cachedir.v

@@ -48 +48 @@
         if (enable)
          if (wren_b)
-            mem2[address_b] <= data_b;
+            mem1[address_b] <= data_b;
      end
-assign  q_b = mem2[address_b];
+assign  q_b = mem1[address_b];
 endmodule

trunk/os2wb/os2wb.v

@@ -125 +125 @@
 
 // sal: escludo test della DRAM `define TEST_DRAM        1
-`define TEST_DRAM        1
+`define TEST_DRAM        0
 `define DEBUGGING        1
 
@@ -344 +344 @@
                cpx_ready<=0;
                cpx_two_packet<=0;
-               inval_vect0[3]<=0;
-               inval_vect1[3]<=0;
+               //inval_vect0[3]<=0;
+               //inval_vect1[3]<=0;
+               inval_vect0<=0;
+               inval_vect1<=0;
                multi_hit<=0;
                multi_hit1<=0;

trunk/sim/simula.do

@@ -2 +2 @@
 
 set DEFINE +define+DEBUG+FPGA_SYN
+#+FPGA_SYN_NO_SPU
 #+FPGA_NEW_IRF
 set INCLUDEDIR +incdir+../T1-common/include/