Legend:
- Unmodified
- Added
- Removed
-
trunk/sw/boot.S
r35 r36 33 33 mov %g0, %o5 34 34 35 35 !wrpr %g0, 0, %gl 36 36 !wrpr %g0, 0, %tl 37 37 -
trunk/sw/linker.lds
r33 r36 6 6 7 7 SECTIONS { 8 .boot 0x 0000000000000020: { *(.boot);}8 .boot 0xf0000020: { *(.boot);} 9 9 .text : { *(.text) } 10 10 .data : { *(.data) } -
trunk/sw/uart.c
r34 r36 1 1 #include "uart.h" 2 2 3 const long UART_BASE_ADR[1] = {0x800000FFF0C2C000}; 4 const int UART_BAUDS[1] = {0}; 3 #define BASE_UART 0x800000FFF0C2C000 4 #define BAUD_UART 100000 5 //const long UART_BASE_ADR[1] = {0x800000FFF0C2C000}; 6 //const int UART_BAUDS[1] = {0}; 5 7 const int BAUD_RATE =100000; 6 8 const int IN_CLK =50000000; … … 12 14 #define WAIT_FOR_XMITR(core) \ 13 15 do { \ 14 lsr = REG8( UART_BASE_ADR[core]+ UART_LSR); \16 lsr = REG8(BASE_UART + UART_LSR); \ 15 17 } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY) 16 18 17 19 #define WAIT_FOR_THRE(core) \ 18 20 do { \ 19 lsr = REG8( UART_BASE_ADR[core]+ UART_LSR); \21 lsr = REG8(BASE_UART + UART_LSR); \ 20 22 } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE) 21 23 22 #define CHECK_FOR_CHAR(core) (REG8( UART_BASE_ADR[core]+ UART_LSR) & UART_LSR_DR)24 #define CHECK_FOR_CHAR(core) (REG8(BASE_UART + UART_LSR) & UART_LSR_DR) 23 25 24 26 #define WAIT_FOR_CHAR(core) \ 25 27 do { \ 26 lsr = REG8( UART_BASE_ADR[core]+ UART_LSR); \28 lsr = REG8(BASE_UART + UART_LSR); \ 27 29 } while ((lsr & UART_LSR_DR) != UART_LSR_DR) 28 30 … … 50 52 */ 51 53 uart_init(0); 54 52 55 for(;;) { 53 56 uart_puts(0,"XOpenSparc is alive \n"); … … 62 65 //float float_divisor; 63 66 /* Reset receiver and transmiter */ 64 REG8( UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; 65 //asm("clr %sp \n"); 67 asm("nop \n"); 68 asm("nop \n"); 69 asm("nop \n"); 70 asm("nop \n"); 71 REG8( BASE_UART + UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; 72 //REG8( UART_BASE_ADR[core] + UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; 73 asm("nop \n"); 74 asm("nop \n"); 75 asm("nop \n"); 76 asm("nop \n"); 77 asm("nop \n"); 66 78 //asm("sethi %hi(8), %sp \n"); 67 79 //asm("mov 0xfff, %sp \n"); 68 80 69 81 /* Disable all interrupts */ 70 REG8(UART_BASE_ADR[core] + UART_IER) = 0x00; 82 REG8(BASE_UART + UART_IER) = 0x00; 83 //REG8(UART_BASE_ADR[core] + UART_IER) = 0x00; 71 84 72 85 /* Set 8 bit char, 1 stop bit, no parity */ 73 REG8( UART_BASE_ADR[core]+ UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);86 REG8(BASE_UART + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY); 74 87 75 88 /* Set baud rate */ … … 79 92 divisor = BAUD_RATE; 80 93 81 REG8( UART_BASE_ADR[core]+ UART_LCR) |= UART_LCR_DLAB;82 REG8( UART_BASE_ADR[core]+ UART_DLL) = divisor & 0x000000ff;83 REG8( UART_BASE_ADR[core]+ UART_DLM) = (divisor >> 8) & 0x000000ff;84 REG8( UART_BASE_ADR[core]+ UART_LCR) &= ~(UART_LCR_DLAB);94 REG8(BASE_UART + UART_LCR) |= UART_LCR_DLAB; 95 REG8(BASE_UART + UART_DLL) = divisor & 0x000000ff; 96 REG8(BASE_UART + UART_DLM) = (divisor >> 8) & 0x000000ff; 97 REG8(BASE_UART + UART_LCR) &= ~(UART_LCR_DLAB); 85 98 86 99 return; … … 92 105 93 106 WAIT_FOR_THRE(core); 94 REG8( UART_BASE_ADR[core]+ UART_TX) = c;107 REG8(BASE_UART + UART_TX) = c; 95 108 if(c == '\n') { 96 109 WAIT_FOR_THRE(core); 97 REG8( UART_BASE_ADR[core]+ UART_TX) = '\r';110 REG8(BASE_UART + UART_TX) = '\r'; 98 111 } 99 112 WAIT_FOR_XMITR(core);
Note: See TracChangeset
for help on using the changeset viewer.