Changeset 36 in XOpenSparcT1 for trunk/sw/uart.c

Timestamp:

04/11/11 09:54:25 (13 years ago)

Author:

pntsvt00

Message:

modificati i file per la compilazione. boot.s linkato a 0xFFF0000020

File:

• trunk/sw/uart.c (modified) (6 diffs)

trunk/sw/uart.c

@@ -1 +1 @@
 #include "uart.h"
 
-const long UART_BASE_ADR[1] = {0x800000FFF0C2C000};
-const int UART_BAUDS[1] = {0};
+#define BASE_UART 0x800000FFF0C2C000 
+#define BAUD_UART 100000 
+//const long UART_BASE_ADR[1] = {0x800000FFF0C2C000};
+//const int UART_BAUDS[1] = {0};
 const int BAUD_RATE =100000;
 const int IN_CLK =50000000;
@@ -12 +14 @@
 #define WAIT_FOR_XMITR(core)                    \
 do { \
-lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+lsr = REG8(BASE_UART + UART_LSR); \
 } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
 #define WAIT_FOR_THRE(core)                     \
 do { \
-lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+lsr = REG8(BASE_UART + UART_LSR); \
 } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
-#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
+#define CHECK_FOR_CHAR(core) (REG8(BASE_UART + UART_LSR) & UART_LSR_DR)
 
 #define WAIT_FOR_CHAR(core)                     \
 do { \
-lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+lsr = REG8(BASE_UART + UART_LSR); \
 } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
@@ -50 +52 @@
 */
         uart_init(0);
+
         for(;;) { 
                 uart_puts(0,"XOpenSparc is alive \n"); 
@@ -62 +65 @@
         //float float_divisor;
         /* Reset receiver and transmiter */
-        REG8( UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
-        //asm("clr %sp \n");    
+        asm("nop \n");  
+        asm("nop \n");  
+        asm("nop \n");  
+        asm("nop \n");
+        REG8( BASE_UART + UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+        //REG8( UART_BASE_ADR[core] + UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+        asm("nop \n");  
+        asm("nop \n");  
+        asm("nop \n");  
+        asm("nop \n");  
+        asm("nop \n");  
         //asm("sethi %hi(8), %sp \n");  
         //asm("mov 0xfff, %sp \n");     
 
         /* Disable all interrupts */
-        REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
+        REG8(BASE_UART + UART_IER) = 0x00;
+        //REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
         
         /* Set 8 bit char, 1 stop bit, no parity */
-        REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
+        REG8(BASE_UART + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
         
         /* Set baud rate */
@@ -79 +92 @@
         divisor = BAUD_RATE;
 
-        REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
-        REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
-        REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
-        REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
+        REG8(BASE_UART + UART_LCR) |= UART_LCR_DLAB;
+        REG8(BASE_UART + UART_DLL) = divisor & 0x000000ff;
+        REG8(BASE_UART + UART_DLM) = (divisor >> 8) & 0x000000ff;
+        REG8(BASE_UART + UART_LCR) &= ~(UART_LCR_DLAB);
         
         return;
@@ -92 +105 @@
         
         WAIT_FOR_THRE(core);
-        REG8(UART_BASE_ADR[core] + UART_TX) = c;
+        REG8(BASE_UART + UART_TX) = c;
         if(c == '\n') {
                 WAIT_FOR_THRE(core);
-                REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
+                REG8(BASE_UART + UART_TX) = '\r';
         }
         WAIT_FOR_XMITR(core);