source:
HDLQ/TestBenches/TB.v
@
1
| Revision 1, 203 bytes checked in by ttvmrc00, 13 years ago (diff) | |
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| 1 | module test_bench; |
| 2 | reg in,fault; |
| 3 | wire out; |
| 4 | |
| 5 | |
| 6 | Inverter INV ( |
| 7 | .in (in), |
| 8 | .out(out), |
| 9 | .fault(fault) |
| 10 | ); |
| 11 | initial |
| 12 | begin |
| 13 | in = 0; |
| 14 | fault = 1; |
| 15 | end |
| 16 | always |
| 17 | #5 in = !in; |
| 18 | |
| 19 | endmodule |
| 20 | |
| 21 |
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