- Timestamp:
- 03/24/11 14:58:51 (14 years ago)
- File:
-
- 1 edited
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trunk/sim/simula.do
r14 r15 13 13 vlog +incdir+../T1-common/include/ ../os2wb/*.v 14 14 vlog +incdir+../T1-common/include/ ../T1-common/m1/*.V 15 vlog + incdir+../T1-common/include/ ../T1-common/srams/*.v15 vlog +define+FPGA_SYN +incdir+../T1-common/include/ ../T1-common/srams/*.v 16 16 vlog +incdir+../T1-common/include/ ../T1-common/u1/*.V 17 17 vlog +incdir+../T1-common/include/ ../T1-FPU/*.v … … 39 39 #Load the design. Use required libraries.# 40 40 41 vsim -c -t ps -novopt +notimingchecks -L unisims_ver work.tb_top glbl41 vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 42 42 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl 43 43
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