- Timestamp:
- 03/24/11 15:05:49 (14 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/sim/tb_top.v
r11 r16 32 32 wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; 33 33 wire [7:0] ddr2_dm_sdram; 34 regddr2_clk_sdram;35 regddr2_clk_n_sdram;36 regddr2_address_sdram;37 reg[2:0] ddr2_ba_sdram;38 regddr2_ras_n_sdram;39 regddr2_cas_n_sdram;40 regddr2_we_n_sdram;41 reg [CS_WIDTH-1:0]ddr2_cs_n_sdram;42 regddr2_cke_sdram;43 reg [ODT_WIDTH-1:0]ddr2_odt_sdram;34 wire ddr2_clk_sdram; 35 wire ddr2_clk_n_sdram; 36 wire ddr2_address_sdram; 37 wire [2:0] ddr2_ba_sdram; 38 wire ddr2_ras_n_sdram; 39 wire ddr2_cas_n_sdram; 40 wire ddr2_we_n_sdram; 41 wire [CS_WIDTH-1:0] ddr2_cs_n_sdram; 42 wire ddr2_cke_sdram; 43 wire [ODT_WIDTH-1:0] ddr2_odt_sdram; 44 44 45 45 wire stx;
Note: See TracChangeset
for help on using the changeset viewer.