- Timestamp:
- 03/25/11 12:19:25 (14 years ago)
- Location:
- trunk
- Files:
-
- 2 added
- 9 edited
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Top/W1.v (modified) (8 diffs)
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WB/wb_conbus_top.v (modified) (1 diff)
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WB2ALTDDR3/dram_wb.v (modified) (7 diffs)
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Xilinx/cachedir.v (modified) (1 diff)
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Xilinx/dram.v (modified) (1 diff)
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os2wb/os2wb.v (modified) (1 diff)
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sim/flash.v (modified) (1 diff)
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sim/simula.do (modified) (2 diffs)
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sim/tb_top.v (modified) (6 diffs)
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tools (added)
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tools/dump2hex.php (added)
Legend:
- Unmodified
- Added
- Removed
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trunk/Top/W1.v
r14 r17 33 33 //output ddr3_reset, 34 34 output [12:0] ddr3_a, 35 output [ 2:0] ddr3_ba,35 output [ 1:0] ddr3_ba, 36 36 output ddr3_ras_n, 37 37 output ddr3_cas_n, … … 92 92 wire pllclk; 93 93 wire sysclk; 94 wire wb_clk_i; 94 95 wire wb_rst_i; 95 96 wire [35:0] CONTROL0; … … 100 101 reg [31:0] cycle_count; 101 102 102 assign flash_clk= 1;103 assign flash_clk=wb_clk_i; 103 104 assign flash_adv=0; 104 105 assign flash_rst=!wb_rst_i; … … 182 183 .m0_err_o(), 183 184 .m0_rty_o(), 184 .m0_cab_i( 0),185 .m0_cab_i(1'b0), 185 186 186 187 //Ethernet … … 197 198 .m1_cab_i(m1_cab_i), 198 199 199 .m2_dat_i( 0),200 .m2_dat_i(64'h0000000000000000), 200 201 .m2_dat_o(), 201 .m2_adr_i( 0),202 .m2_sel_i( 0),203 .m2_we_i( 0),204 .m2_cyc_i( 0),205 .m2_stb_i( 0),202 .m2_adr_i(64'h0000000000000000), 203 .m2_sel_i(8'h00), 204 .m2_we_i(1'b0), 205 .m2_cyc_i(1'b0), 206 .m2_stb_i(1'b0), 206 207 .m2_ack_o(), 207 208 .m2_err_o(), 208 209 .m2_rty_o(), 209 .m2_cab_i( 0),210 .m2_cab_i(1'b0), 210 211 211 212 .m3_dat_i(0), … … 426 427 ); 427 428 428 WBFLASH flash (429 WBFLASH flash_inst ( 429 430 .wb_clk_i(wb_clk_i), 430 431 .wb_rst_i(wb_rst_i), … … 477 478 .srx_pad_i(srx), 478 479 .rts_pad_o(), 479 .cts_pad_i(1 ),480 .cts_pad_i(1'b1), 480 481 .dtr_pad_o(), 481 .dsr_pad_i(1 ),482 .ri_pad_i( 0),483 .dcd_pad_i(1 ),484 482 .dsr_pad_i(1'b1), 483 .ri_pad_i(1'b0), 484 .dcd_pad_i(1'b1), 485 .baud_o(baud_o) 485 486 ); 486 487 … … 585 586 ); 586 587 587 assign wb_rst_i=(!dcm_locked || !phy_init_done); 588 assign wb_rst_i=(!dcm_locked ); //FIXME 589 //assign wb_rst_i=(!dcm_locked || !phy_init_done); //FIXME 588 590 589 591 //reg [223:0] ILA_DATA; -
trunk/WB/wb_conbus_top.v
r6 r17 133 133 134 134 135 //parameter s0_addr_w = 1 ; // slave 0 address decode width 136 //parameter s0_addr = 1'b0; // slave 0 address 137 //parameter s1_addr_w = 41 ; // slave 1 address decode width 138 //parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address 135 139 parameter s0_addr_w = 1 ; // slave 0 address decode width 136 parameter s0_addr = 1'b0; // slave 0 address 140 parameter s0_addr = 1'b1; // slave 0 address 141 137 142 parameter s1_addr_w = 41 ; // slave 1 address decode width 138 parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address 143 parameter s1_addr = {40'h0000000000,1'b0}; // slave 1 address 144 139 145 parameter s2_addr_w = 56 ; 140 146 parameter s2_addr = {56'h800000FFF0C2C1}; // slave 2 address -
trunk/WB2ALTDDR3/dram_wb.v
r10 r17 47 47 //output ddr3_reset, 48 48 output [12:0] ddr3_a, 49 output [ 2:0] ddr3_ba,49 output [ 1:0] ddr3_ba, 50 50 output ddr3_ras_n, 51 51 output ddr3_cas_n, … … 64 64 ); 65 65 66 wire [ 255:0] rd_data_fifo_out;66 wire [127:0] rd_data_fifo_out; 67 67 reg [ 23:0] rd_addr_cache; 68 wire [ 71:0] wr_dout;68 wire [127:0] wr_dout; 69 69 wire [ 31:0] cmd_out; 70 70 reg wb_stb_i_d; 71 reg [ 31:0] mask_data;71 reg [ 15:0] mask_data; 72 72 73 73 wire dram_ready; … … 83 83 .phy_init_done(phy_init_done), 84 84 .app_wdf_mask_data(mask_data), 85 .app_af_addr(cmd_out[ 25:2]),85 .app_af_addr(cmd_out[31:1]), 86 86 .rd_data_valid(rd_data_valid), 87 87 .rd_data_fifo_out(rd_data_fifo_out), 88 .app_wdf_data(wr_dout[ 63:0]),88 .app_wdf_data(wr_dout[127:0]), 89 89 90 90 // in dubbio … … 96 96 .clk0_tb(), 97 97 .idly_clk_200(clk200), 98 //.rst0_tb(ddr3_reset),98 .rst0_tb(ddr3_reset), 99 99 100 100 .ddr2_dqs(ddr3_dqs), … … 110 110 .ddr2_we_n(ddr3_we_n), 111 111 .ddr2_ba(ddr3_ba), 112 112 .ddr2_a(ddr3_a), 113 113 .ddr2_dm(ddr3_dm) 114 114 // | … … 178 178 ); 179 179 */ 180 180 181 assign ddr_rst=!phy_init_done; 181 182 … … 299 300 reg rd_data_valid_stb_d3; 300 301 reg rd_data_valid_stb_d4; 301 reg [ 255:0] rd_data_fifo_out_d;302 reg [127:0] rd_data_fifo_out_d; 302 303 reg wb_ack_d; 303 304 -
trunk/Xilinx/cachedir.v
r10 r17 23 23 input enable, 24 24 input wren_a, 25 input [ 7:0] address_a,25 input [ 8:0] address_a, 26 26 input [28:0] data_a, 27 27 output [ 28:0] q_a, 28 28 input wren_b, 29 input [ 7:0] address_b,29 input [ 8:0] address_b, 30 30 input [28:0] data_b, 31 31 output [28:0] q_b 32 32 ); 33 33 34 reg [28:0] mem1 [(2** 7)-1:0];35 reg [28:0] mem2 [(2** 7)-1:0];34 reg [28:0] mem1 [(2**8)-1:0]; 35 reg [28:0] mem2 [(2**8)-1:0]; 36 36 37 37 always @(posedge clock) -
trunk/Xilinx/dram.v
r10 r17 74 74 parameter CKE_WIDTH = 1, 75 75 // # of memory clock enable outputs. 76 parameter CLK_WIDTH = 2,76 parameter CLK_WIDTH = 1, 77 77 // # of clock outputs. 78 78 parameter COL_WIDTH = 10, -
trunk/os2wb/os2wb.v
r14 r17 1231 1231 .enable(dir_en), 1232 1232 .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init), 1233 .address_a({ 1'b0,icache_index}),1233 .address_a({2'b0,icache_index}), 1234 1234 .data_a(icache_data), 1235 1235 .q_a(icache0_do), 1236 1236 1237 1237 .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), 1238 .address_b({ 1'b1,icache_index}),1238 .address_b({2'b01,icache_index}), 1239 1239 .data_b(icache_data), 1240 1240 .q_b(icache1_do) -
trunk/sim/flash.v
r12 r17 25 25 26 26 // Parameters 27 parameter addr_bits = 2 0;27 parameter addr_bits = 22; 28 28 parameter addr_max = (1<<addr_bits)-1; 29 29 parameter memfilename = "memory.hex"; -
trunk/sim/simula.do
r15 r17 32 32 vlog $env(XILINX)/../../verilog/src/glbl.v 33 33 #vlog $XILINX/../../verilog/src/glbl.v 34 vlog ../sim/*.v34 vlog +define+DEBUG ../sim/*.v 35 35 36 36 #Pass the parameters for memory model parameter file# … … 39 39 #Load the design. Use required libraries.# 40 40 41 vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 41 42 vsim -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 43 44 #vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 42 45 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl 43 46 -
trunk/sim/tb_top.v
r16 r17 32 32 wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; 33 33 wire [7:0] ddr2_dm_sdram; 34 wire ddr2_clk_sdram;35 wire ddr2_clk_n_sdram;36 wire 37 wire [ 2:0]ddr2_ba_sdram;34 wire ddr2_clk_sdram; 35 wire ddr2_clk_n_sdram; 36 wire [12:0] ddr2_address_sdram; 37 wire [1:0] ddr2_ba_sdram; 38 38 wire ddr2_ras_n_sdram; 39 39 wire ddr2_cas_n_sdram; … … 45 45 wire stx; 46 46 wire srx; 47 48 wire [21:0] flash_addr; 49 wire [15:0] flash_data; 50 51 47 52 48 53 initial begin … … 60 65 // #1000 61 66 // sys_reset <= 1'b0; 62 # 4900067 #100000 63 68 $display("INFO: TBENCH: Completed simulation!"); 64 69 $finish; … … 101 106 ( 102 107 .clk_in (clk_in), 103 .sysrst (sys rsti_out),108 .sysrst (sys_rst_out), 104 109 105 110 // ddr3 memory interface … … 110 115 .ddr3_ck_n (ddr2_clk_n_sdram), 111 116 .ddr3_a (ddr2_address_sdram), 112 .ddr3_ba (ddr2_ba_sdram), 117 .ddr3_ba (ddr2_ba_sdram), //FIXME 113 118 .ddr3_ras_n (ddr2_ras_n_sdram), 114 119 .ddr3_cas_n (ddr2_cas_n_sdram), … … 164 169 .we_n (ddr2_we_n_sdram), 165 170 .dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), 166 .ba (ddr2_ba_sdram), 171 .ba (ddr2_ba_sdram), //FIXME 167 172 .addr (ddr2_address_sdram), 168 173 .dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
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