Changeset 17 in XOpenSparcT1 for trunk/sim/simula.do
- Timestamp:
- 03/25/11 12:19:25 (14 years ago)
- File:
-
- 1 edited
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trunk/sim/simula.do
r15 r17 32 32 vlog $env(XILINX)/../../verilog/src/glbl.v 33 33 #vlog $XILINX/../../verilog/src/glbl.v 34 vlog ../sim/*.v34 vlog +define+DEBUG ../sim/*.v 35 35 36 36 #Pass the parameters for memory model parameter file# … … 39 39 #Load the design. Use required libraries.# 40 40 41 vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 41 42 vsim -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 43 44 #vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl 42 45 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl 43 46
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