Changeset 17 in XOpenSparcT1 for trunk/sim/tb_top.v

Timestamp:

03/25/11 12:19:25 (14 years ago)

Author:

pntsvt00

Message:

la simulazione legge dalla flash

File:

• trunk/sim/tb_top.v (modified) (6 diffs)

trunk/sim/tb_top.v

@@ -32 +32 @@
    wire [DQS_WIDTH-1:0]         ddr2_dqs_n_sdram;
    wire [7:0]                   ddr2_dm_sdram;
-   wire                         ddr2_clk_sdram;
-   wire                         ddr2_clk_n_sdram;
-   wire                         ddr2_address_sdram;
-   wire [2:0]                   ddr2_ba_sdram;
+   wire                                  ddr2_clk_sdram;
+   wire                                     ddr2_clk_n_sdram;
+   wire [12:0]                                ddr2_address_sdram;
+   wire [1:0]                           ddr2_ba_sdram;
    wire                         ddr2_ras_n_sdram;
    wire                         ddr2_cas_n_sdram;
@@ -45 +45 @@
    wire                          stx;
    wire                          srx;
+   
+   wire [21:0]                    flash_addr; 
+   wire [15:0]                    flash_data;
+   
+
    
    initial begin
@@ -60 +65 @@
     //     #1000
     //     sys_reset <= 1'b0;
-         #49000
+         #100000
          $display("INFO: TBENCH: Completed simulation!");
          $finish;
@@ -101 +106 @@
 (
    .clk_in (clk_in),
-   .sysrst (sysrsti_out),
+   .sysrst (sys_rst_out),
 
    // ddr3 memory interface
@@ -110 +115 @@
    .ddr3_ck_n (ddr2_clk_n_sdram),
    .ddr3_a (ddr2_address_sdram),
-   .ddr3_ba (ddr2_ba_sdram),
+   .ddr3_ba (ddr2_ba_sdram), //FIXME
    .ddr3_ras_n (ddr2_ras_n_sdram),
    .ddr3_cas_n (ddr2_cas_n_sdram),
@@ -164 +169 @@
                       .we_n      (ddr2_we_n_sdram),
                       .dm_rdqs   (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
-                      .ba        (ddr2_ba_sdram),
+                      .ba        (ddr2_ba_sdram), //FIXME
                       .addr      (ddr2_address_sdram),
                       .dq        (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),