- Timestamp:
- 04/06/11 20:11:32 (14 years ago)
- File:
-
- 1 edited
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Library/MajorityVoter.v
r1 r2 13 13 assign out = (fault0) ? wi3: wi2; 14 14 endmodule 15 16 17 18 19 20 21 22 23 24
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