- Timestamp:
- 04/01/11 10:30:46 (14 years ago)
- Location:
- trunk
- Files:
-
- 2 added
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/Top/W1.v
r22 r23 406 406 .wb_rty_o(s0_rty_i), 407 407 .wb_cab_i(s0_cab_o), 408 .ddr 3_dq(ddr3_dq),409 .ddr 3_dqs(ddr3_dqs),410 .ddr 3_dqs_n(ddr3_dqs_n),411 .ddr 3_ck(ddr3_ck),412 .ddr 3_ck_n(ddr3_ck_n),408 .ddr2_dq(ddr3_dq), 409 .ddr2_dqs(ddr3_dqs), 410 .ddr2_dqs_n(ddr3_dqs_n), 411 .ddr2_ck(ddr3_ck), 412 .ddr2_ck_n(ddr3_ck_n), 413 413 //.ddr3_reset(ddr3_reset), 414 .ddr 3_a(ddr3_a),415 .ddr 3_ba(ddr3_ba),416 .ddr 3_ras_n(ddr3_ras_n),417 .ddr 3_cas_n(ddr3_cas_n),418 .ddr 3_we_n(ddr3_we_n),419 .ddr 3_cs_n(ddr3_cs_n),420 .ddr 3_odt(ddr3_odt),421 .ddr 3_ce(ddr3_ce),422 .ddr 3_dm(ddr3_dm),414 .ddr2_a(ddr3_a), 415 .ddr2_ba(ddr3_ba), 416 .ddr2_ras_n(ddr3_ras_n), 417 .ddr2_cas_n(ddr3_cas_n), 418 .ddr2_we_n(ddr3_we_n), 419 .ddr2_cs_n(ddr3_cs_n), 420 .ddr2_odt(ddr3_odt), 421 .ddr2_ce(ddr3_ce), 422 .ddr2_dm(ddr3_dm), 423 423 .phy_init_done(phy_init_done), 424 424 .dcm_locked(dcm_locked), -
trunk/WB2ALTDDR3/dram_wb.v
r22 r23 40 40 input wb_cab_i, 41 41 42 inout [63:0] ddr 3_dq,43 inout [ 7:0] ddr 3_dqs,44 inout [ 7:0] ddr 3_dqs_n,45 inout ddr 3_ck,46 inout ddr 3_ck_n,42 inout [63:0] ddr2_dq, 43 inout [ 7:0] ddr2_dqs, 44 inout [ 7:0] ddr2_dqs_n, 45 inout ddr2_ck, 46 inout ddr2_ck_n, 47 47 //output ddr3_reset, 48 output [12:0] ddr 3_a,49 output [ 1:0] ddr 3_ba,50 output ddr 3_ras_n,51 output ddr 3_cas_n,52 output ddr 3_we_n,53 output ddr 3_cs_n,54 output ddr 3_odt,55 output ddr 3_ce,56 output [ 7:0] ddr 3_dm,48 output [12:0] ddr2_a, 49 output [ 1:0] ddr2_ba, 50 output ddr2_ras_n, 51 output ddr2_cas_n, 52 output ddr2_we_n, 53 output ddr2_cs_n, 54 output ddr2_odt, 55 output ddr2_ce, 56 output [ 7:0] ddr2_dm, 57 57 58 58 output phy_init_done, … … 74 74 wire dram_ready; 75 75 wire fifo_empty; 76 reg push_tran; 76 reg push_tran_wdf; 77 reg push_tran; 77 78 78 79 //wire [13:0] parallelterminationcontrol; … … 85 86 //synthesis traslate on 86 87 ) 87 dram_ctrl( 88 // cmd_out[31] è il WE, CMD_OUT[30:0] corrisponde ad wb_addr[33:3] 89 dram_ctrl( 88 90 .sys_clk(clk200), 89 91 .sys_rst_n(sysrst), // Resets all … … 93 95 .app_af_addr(cmd_out[30:0]), 94 96 .app_af_wren(push_tran), //write enable for address fifo 95 .app_wdf_wren( cmd_out[31] & push_tran), // write enable for write data fifo97 .app_wdf_wren(push_tran_wdf), // write enable for write data fifo 96 98 .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}), 97 99 .app_wdf_mask_data(mask_data), … … 106 108 .idly_clk_200(clk200), 107 109 108 .ddr2_ck(ddr 3_ck),109 .ddr2_ck_n(ddr 3_ck_n),110 .ddr2_dq(ddr 3_dq),111 .ddr2_dqs(ddr 3_dqs),112 .ddr2_dqs_n(ddr 3_dqs_n),113 .ddr2_ras_n(ddr 3_ras_n),114 .ddr2_cas_n(ddr 3_cas_n),115 .ddr2_odt(ddr 3_odt),116 .ddr2_cs_n(ddr 3_cs_n),117 .ddr2_cke(ddr 3_ce),118 .ddr2_we_n(ddr 3_we_n),119 .ddr2_ba(ddr 3_ba),120 .ddr2_a(ddr 3_a),121 .ddr2_dm(ddr 3_dm)110 .ddr2_ck(ddr2_ck), 111 .ddr2_ck_n(ddr2_ck_n), 112 .ddr2_dq(ddr2_dq), 113 .ddr2_dqs(ddr2_dqs), 114 .ddr2_dqs_n(ddr2_dqs_n), 115 .ddr2_ras_n(ddr2_ras_n), 116 .ddr2_cas_n(ddr2_cas_n), 117 .ddr2_odt(ddr2_odt), 118 .ddr2_cs_n(ddr2_cs_n), 119 .ddr2_cke(ddr2_ce), 120 .ddr2_we_n(ddr2_we_n), 121 .ddr2_ba(ddr2_ba), 122 .ddr2_a(ddr2_a), 123 .ddr2_dm(ddr2_dm) 122 124 ); 123 125 … … 189 191 190 192 always @( * ) 191 case(cmd_out[0]) 192 1'b0:mask_data<={8'h00,wr_dout[71:64]}; 193 1'b1:mask_data<={wr_dout[71:64],8'h00}; 193 case(push_tran & cmd_out[31]) 194 1'b1:mask_data<=16'hffff; 195 1'b0:mask_data<={wr_dout[71:64],8'h00}; 196 //1'b1:mask_data<={wr_dout[71:64] ^ 8'hff,8'hff}; FIXME il sel e' in logica negata 194 197 endcase 198 199 //always @( * ) 200 // case(cmd_out[0]) 201 // 1'b0:mask_data<={8'h00,wr_dout[71:64]}; 202 // 1'b1:mask_data<={wr_dout[71:64],8'h00}; 203 // endcase 195 204 196 205 //wire [254:0] trig0; … … 217 226 reg fifo_full_d; 218 227 reg written; 219 reg 220 221 dram_fifo fifo(228 reg fifo_read; 229 230 dram_fifo_fall fifo( 222 231 .rst(ddr_rst), 223 232 .wr_clk(wb_clk_i), … … 235 244 `define DDR_WRITE_1 3'b001 236 245 `define DDR_WRITE_2 3'b010 246 `define DDR_WRITE_3 3'b110 237 247 `define DDR_READ_1 3'b011 238 248 `define DDR_READ_2 3'b100 … … 242 252 reg wb_ack_d1; 243 253 254 //FIXME si perde il primo comando di scrittura 244 255 always @(posedge ddr_clk or posedge ddr_rst) 245 256 if(ddr_rst) … … 247 258 ddr_state<=`DDR_IDLE; 248 259 fifo_read<=0; 260 push_tran_wdf<=0; 249 261 push_tran<=0; 250 262 rd_data_valid_stb<=0; … … 255 267 if(!fifo_empty && dram_ready) 256 268 begin 257 push_tran<=1;258 269 if(cmd_out[31]) 259 270 begin 271 push_tran_wdf<=1; 260 272 ddr_state<=`DDR_WRITE_1; 261 fifo_read<=1;262 273 end 263 274 else 275 begin 276 push_tran<=1; 264 277 ddr_state<=`DDR_READ_1; 265 end 278 end 279 end 266 280 `DDR_WRITE_1: 267 281 begin 268 push_tran<=0; 269 fifo_read<=0; 282 fifo_read<=1; 283 push_tran_wdf<=1; 284 push_tran<=1; 270 285 ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency 271 286 end 272 287 `DDR_WRITE_2: 273 ddr_state<=`DDR_IDLE; 288 begin 289 fifo_read<=0; 290 push_tran_wdf<=0; 291 push_tran<=0; 292 ddr_state<=`DDR_WRITE_3; 293 end 294 `DDR_WRITE_3: 295 ddr_state<=`DDR_IDLE; 274 296 `DDR_READ_1: 275 297 begin … … 297 319 reg rd_data_valid_stb_d3; 298 320 reg rd_data_valid_stb_d4; 299 reg [127:0] rd_data_fifo_out_d; 321 reg [127:0] rd_data_fifo_out_dH; 322 reg [127:0] rd_data_fifo_out_dL; 300 323 reg wb_ack_d; 301 324 302 325 always @( * ) 303 case(wb_adr_i[3]) 304 1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0]; 305 1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64]; 326 case(wb_adr_i[4:3]) 327 2'b00:wb_dat_o<=rd_data_fifo_out_dL[63:0]; 328 2'b01:wb_dat_o<=rd_data_fifo_out_dL[127:64]; 329 2'b10:wb_dat_o<=rd_data_fifo_out_dH[63:0]; 330 2'b11:wb_dat_o<=rd_data_fifo_out_dH[127:64]; 306 331 endcase 307 332 … … 340 365 wb_ack_d1<=wb_ack_d; 341 366 if(rd_data_valid) 342 rd_data_fifo_out_d<=rd_data_fifo_out; 367 rd_data_fifo_out_dH<=rd_data_fifo_out; 368 if(rd_data_valid && !rd_data_valid_stb) 369 rd_data_fifo_out_dL<=rd_data_fifo_out; 370 343 371 end 344 372 345 373 endmodule 374 -
trunk/os2wb/os2wb.v
r22 r23 121 121 //`define MEM_SIZE 64'h00000000_10000000 //256 MB 122 122 //`define MEM_SIZE 64'h00000000_00100000 //1MB 123 `define MEM_SIZE 64'h00000000_0000 1000 //256KB123 `define MEM_SIZE 64'h00000000_00000100 //1KB 124 124 125 125 // sal: escludo test della DRAM `define TEST_DRAM 1 … … 278 278 if(wb_addr<`MEM_SIZE-8) 279 279 begin 280 if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]})281 begin280 //if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]}) 281 // begin 282 282 wb_addr[31:0]<=wb_addr[31:0]+8; 283 283 state<=`TEST_DRAM_3; 284 end285 else286 $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time);287 284 // end 285 //else 286 // $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); 287 $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); 288 288 end 289 289 else -
trunk/sim/tb_top.v
r22 r23 87 87 // #1000 88 88 // sys_reset <= 1'b0; 89 #700_000 89 // #700_000 90 #374_600 90 91 $display("INFO: TBENCH: Completed simulation!"); 91 92 $finish;
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