- Timestamp:
- 03/31/11 12:31:26 (14 years ago)
- Location:
- trunk
- Files:
-
- 2 deleted
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/NOR-flash/WBFLASH.v
r8 r22 155 155 156 156 assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1); 157 assign flash_wen= 1;157 assign flash_wen= !wb_we_i; 158 158 assign flash_cen=0; 159 159 -
trunk/T1-common/srams/bw_r_icd.v
r6 r22 191 191 .q (wrdata_f), 192 192 .en ((~sehold)), 193 .se (se)); 193 .se (se), 194 .si (), 195 .so()); 194 196 195 197 always @(posedge clk) begin -
trunk/T1-common/srams/bw_r_irf.v
r6 r22 1185 1185 .clk (clk), 1186 1186 .q (ifu_exu_ren1_d), 1187 .se (se)); 1187 .se (se), 1188 .si (), 1189 .so ()); 1188 1190 dff_s dff_ren2_s2d( 1189 1191 .din (ren2_s), 1190 1192 .clk (clk), 1191 1193 .q (ifu_exu_ren2_d), 1192 .se (se)); 1194 .se (se), 1195 .si (), 1196 .so ()); 1193 1197 dff_s dff_ren3_s2d( 1194 1198 .din (ren3_s), 1195 1199 .clk (clk), 1196 1200 .q (ifu_exu_ren3_d), 1197 .se (se)); 1201 .se (se), 1202 .si (), 1203 .so ()); 1198 1204 dff_s #(5) dff_rs1_s2d( 1199 1205 .din (rs1_s[4:0]), 1200 1206 .clk (clk), 1201 1207 .q (ifu_exu_rs1_d[4:0]), 1202 .se (se)); 1208 .se (se), 1209 .si (), 1210 .so ()); 1203 1211 dff_s #(5) dff_rs2_s2d( 1204 1212 .din (rs2_s[4:0]), 1205 1213 .clk (clk), 1206 1214 .q (ifu_exu_rs2_d[4:0]), 1207 .se (se)); 1215 .se (se), 1216 .si (), 1217 .so ()); 1208 1218 dff_s #(5) dff_rs3_s2d( 1209 1219 .din (rs3_s[4:0]), 1210 1220 .clk (clk), 1211 1221 .q (ifu_exu_rs3_d[4:0]), 1212 .se (se)); 1222 .se (se), 1223 .si (), 1224 .so ()); 1213 1225 dff_s #(2) dff_thr_s2d( 1214 1226 .din (tid_s[1:0]), 1215 1227 .clk (clk), 1216 1228 .q (ifu_exu_thr_d[1:0]), 1217 .se (se)); 1229 .se (se), 1230 .si (), 1231 .so ()); 1218 1232 dff_s #(2) dff_thr_g2w2( 1219 1233 .din (tid_g[1:0]), 1220 1234 .clk (clk), 1221 1235 .q (ecl_irf_tid_w2[1:0]), 1222 .se (se)); 1236 .se (se), 1237 .si (), 1238 .so ()); 1223 1239 dff_s #(2) dff_thr_m2w( 1224 1240 .din (tid_m[1:0]), 1225 1241 .clk (clk), 1226 1242 .q (ecl_irf_tid_w[1:0]), 1227 .se (se)); 1243 .se (se), 1244 .si (), 1245 .so ()); 1228 1246 dff_s #(5) dff_rd_m2w( 1229 1247 .din (rd_m[4:0]), 1230 1248 .clk (clk), 1231 1249 .q (ecl_irf_rd_w[4:0]), 1232 .se (se)); 1250 .se (se), 1251 .si (), 1252 .so ()); 1233 1253 dff_s #(5) dff_rd_g2w2( 1234 1254 .din (rd_g[4:0]), 1235 1255 .clk (clk), 1236 1256 .q (ecl_irf_rd_w2[4:0]), 1237 .se (se)); 1257 .se (se), 1258 .si (), 1259 .so ()); 1238 1260 bw_r_irf_core bw_r_irf_core( 1239 1261 .clk (clk), -
trunk/Top/W1.v
r17 r22 210 210 .m2_cab_i(1'b0), 211 211 212 .m3_dat_i( 0),212 .m3_dat_i(64'h0000000000000000), 213 213 .m3_dat_o(), 214 .m3_adr_i( 0),215 .m3_sel_i( 0),216 .m3_we_i( 0),217 .m3_cyc_i( 0),218 .m3_stb_i( 0),214 .m3_adr_i(64'h0000000000000000), 215 .m3_sel_i(8'h00), 216 .m3_we_i(1'b0), 217 .m3_cyc_i(1'b0), 218 .m3_stb_i(1'b0), 219 219 .m3_ack_o(), 220 220 .m3_err_o(), 221 221 .m3_rty_o(), 222 .m3_cab_i( 0),223 224 .m4_dat_i( 0),222 .m3_cab_i(1'b0), 223 224 .m4_dat_i(64'h0000000000000000), 225 225 .m4_dat_o(), 226 .m4_adr_i( 0),227 .m4_sel_i( 0),228 .m4_we_i( 0),229 .m4_cyc_i( 0),230 .m4_stb_i( 0),226 .m4_adr_i(64'h0000000000000000), 227 .m4_sel_i(8'h00), 228 .m4_we_i(1'b0), 229 .m4_cyc_i(1'b0), 230 .m4_stb_i(1'b0), 231 231 .m4_ack_o(), 232 232 .m4_err_o(), 233 233 .m4_rty_o(), 234 .m4_cab_i( 0),235 236 .m5_dat_i( 0),234 .m4_cab_i(1'b0), 235 236 .m5_dat_i(64'h0000000000000000), 237 237 .m5_dat_o(), 238 .m5_adr_i( 0),239 .m5_sel_i( 0),240 .m5_we_i( 0),241 .m5_cyc_i( 0),242 .m5_stb_i( 0),238 .m5_adr_i(64'h0000000000000000), 239 .m5_sel_i(8'h00), 240 .m5_we_i(1'b0), 241 .m5_cyc_i(1'b0), 242 .m5_stb_i(1'b0), 243 243 .m5_ack_o(), 244 244 .m5_err_o(), 245 245 .m5_rty_o(), 246 .m5_cab_i( 0),247 248 .m6_dat_i( 0),246 .m5_cab_i(1'b0), 247 248 .m6_dat_i(64'h0000000000000000), 249 249 .m6_dat_o(), 250 .m6_adr_i( 0),251 .m6_sel_i( 0),252 .m6_we_i( 0),253 .m6_cyc_i( 0),254 .m6_stb_i( 0),250 .m6_adr_i(64'h0000000000000000), 251 .m6_sel_i(8'h00), 252 .m6_we_i(1'b0), 253 .m6_cyc_i(1'b0), 254 .m6_stb_i(1'b0), 255 255 .m6_ack_o(), 256 256 .m6_err_o(), 257 257 .m6_rty_o(), 258 .m6_cab_i( 0),259 260 .m7_dat_i( 0),258 .m6_cab_i(1'b0), 259 260 .m7_dat_i(64'h0000000000000000), 261 261 .m7_dat_o(), 262 .m7_adr_i( 0),263 .m7_sel_i( 0),264 .m7_we_i( 0),265 .m7_cyc_i( 0),266 .m7_stb_i( 0),262 .m7_adr_i(64'h0000000000000000), 263 .m7_sel_i(8'h00), 264 .m7_we_i(1'b0), 265 .m7_cyc_i(1'b0), 266 .m7_stb_i(1'b0), 267 267 .m7_ack_o(), 268 268 .m7_err_o(), 269 269 .m7_rty_o(), 270 .m7_cab_i( 0),270 .m7_cab_i(1'b0), 271 271 272 272 //DRAM … … 279 279 .s0_stb_o(s0_stb_o), 280 280 .s0_ack_i(s0_ack_i), 281 .s0_err_i( 0),282 .s0_rty_i( 0),281 .s0_err_i(1'b0), 282 .s0_rty_i(1'b0), 283 283 .s0_cab_o(), 284 284 … … 335 335 .s4_cab_o(s4_cab_o), 336 336 337 .s5_dat_i( 0),337 .s5_dat_i(64'h0000000000000000), 338 338 .s5_dat_o(), 339 339 .s5_adr_o(), … … 342 342 .s5_cyc_o(), 343 343 .s5_stb_o(), 344 .s5_ack_i( 0),345 .s5_err_i( 0),346 .s5_rty_i( 0),344 .s5_ack_i(1'b0), 345 .s5_err_i(1'b0), 346 .s5_rty_i(1'b0), 347 347 .s5_cab_o(), 348 348 349 .s6_dat_i( 0),349 .s6_dat_i(64'h0000000000000000), 350 350 .s6_dat_o(), 351 351 .s6_adr_o(), … … 354 354 .s6_cyc_o(), 355 355 .s6_stb_o(), 356 .s6_ack_i( 0),357 .s6_err_i( 0),358 .s6_rty_i( 0),356 .s6_ack_i(1'b0), 357 .s6_err_i(1'b0), 358 .s6_rty_i(1'b0), 359 359 .s6_cab_o(), 360 360 361 .s7_dat_i( 0),361 .s7_dat_i(64'h0000000000000000), 362 362 .s7_dat_o(), 363 363 .s7_adr_o(), … … 366 366 .s7_cyc_o(), 367 367 .s7_stb_o(), 368 .s7_ack_i( 0),369 .s7_err_i( 0),370 .s7_rty_i( 0),368 .s7_ack_i(1'b0), 369 .s7_err_i(1'b0), 370 .s7_rty_i(1'b0), 371 371 .s7_cab_o() 372 372 ); -
trunk/WB/wb_conbus_top.v
r17 r22 133 133 134 134 135 //parameter s0_addr_w = 1 ; // slave 0 address decode width 136 //parameter s0_addr = 1'b0; // slave 0 address 137 //parameter s1_addr_w = 41 ; // slave 1 address decode width 138 //parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address 135 // address for DDR from 0x0 to 0x7fffffff_ffffffff (64'h00000000_00000000 to 64'h7fffffff_ffffffff) 139 136 parameter s0_addr_w = 1 ; // slave 0 address decode width 140 parameter s0_addr = 1'b1; // slave 0 address 141 137 parameter s0_addr = 1'b0; // slave 0 address 138 139 //address for a 32MB flash from 0x800000ff_f0800000 to 0x800000ff_f0ffffff 140 //Check address_w 141 // 32 MB --> 8 MW X32 bits --> 2^23 --> addr_w=64-23=41 142 142 parameter s1_addr_w = 41 ; // slave 1 address decode width 143 parameter s1_addr = {40'h 0000000000,1'b0}; // slave 1 address143 parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address 144 144 145 145 parameter s2_addr_w = 56 ; 146 parameter s2_addr = {56'h800000FFF0C2C1}; // slave 2 address146 parameter s2_addr = {56'h800000FFF0C2C1}; // slave 2 address 147 147 parameter s3_addr_w = 60 ; 148 148 parameter s3_addr = {60'h800000FFF0C2C00}; // slave 3 address 149 149 parameter s4_addr_w = 37 ; 150 parameter s4_addr = {36'h800000FFF,1'b1}; // slave 4 address150 parameter s4_addr = {36'h800000FFF,1'b1}; // slave 4 address 151 151 parameter s5_addr_w = 60 ; 152 152 parameter s5_addr = {60'h400000F00000000}; // slave 5 address -
trunk/WB2ALTDDR3/dram_wb.v
r17 r22 22 22 module dram_wb( 23 23 input clk200, 24 input rup,25 input rdn,24 // input rup, 25 // input rdn, 26 26 27 27 input wb_clk_i, … … 64 64 ); 65 65 66 wire app_af_afull; 66 67 wire [127:0] rd_data_fifo_out; 67 68 reg [ 23:0] rd_addr_cache; 68 wire [ 127:0] wr_dout;69 wire [ 71:0] wr_dout; 69 70 wire [ 31:0] cmd_out; 70 71 reg wb_stb_i_d; … … 78 79 //wire [13:0] seriesterminationcontrol; 79 80 80 dram dram_ctrl( 81 dram # 82 ( 83 //synthesis traslate off 84 .SIM_ONLY (1) 85 //synthesis traslate on 86 ) 87 dram_ctrl( 81 88 .sys_clk(clk200), 82 89 .sys_rst_n(sysrst), // Resets all 83 90 .phy_init_done(phy_init_done), 91 92 .app_af_cmd({2'b00,!cmd_out[31]}), //command for the controller 000:write 001:read 93 .app_af_addr(cmd_out[30:0]), 94 .app_af_wren(push_tran), //write enable for address fifo 95 .app_wdf_wren(cmd_out[31] & push_tran), // write enable for write data fifo 96 .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}), 84 97 .app_wdf_mask_data(mask_data), 85 .app_af_addr(cmd_out[31:1]),98 86 99 .rd_data_valid(rd_data_valid), 87 100 .rd_data_fifo_out(rd_data_fifo_out), 88 .app_wdf_data(wr_dout[127:0]), 89 90 // in dubbio 91 .app_wdf_wren(1'b1), 92 .app_af_wren(1'b1), 93 .app_af_afull(), 94 .app_wdf_afull(), 95 .app_af_cmd(), 96 .clk0_tb(), 97 .idly_clk_200(clk200), 98 .rst0_tb(ddr3_reset), 99 100 .ddr2_dqs(ddr3_dqs), 101 .ddr2_dqs_n(ddr3_dqs_n), 101 102 .clk0_tb(ddr_clk), 103 .rst0_tb(ddr3_reset), 104 .app_af_afull(app_af_afull), 105 .app_wdf_afull(), 106 .idly_clk_200(clk200), 107 102 108 .ddr2_ck(ddr3_ck), 103 109 .ddr2_ck_n(ddr3_ck_n), 104 110 .ddr2_dq(ddr3_dq), 111 .ddr2_dqs(ddr3_dqs), 112 .ddr2_dqs_n(ddr3_dqs_n), 105 113 .ddr2_ras_n(ddr3_ras_n), 106 114 .ddr2_cas_n(ddr3_cas_n), … … 112 120 .ddr2_a(ddr3_a), 113 121 .ddr2_dm(ddr3_dm) 114 // |115 //non sostituiti\|/116 // V117 // .phy_clk(ddr_clk), // User clock118 // .local_ready(dram_ready),119 // .local_burstbegin(push_tran),120 // .local_read_req(!cmd_out[31] && push_tran),121 // .local_write_req(cmd_out[31] && push_tran),122 // .local_wdata({wr_dout[63:0],wr_dout[63:0],wr_dout[63:0],wr_dout[63:0]}),123 // .local_size(3'b001)124 125 122 ); 123 124 assign dram_ready = phy_init_done && !app_af_afull; 126 125 127 126 /* comment by sal … … 179 178 */ 180 179 181 assign ddr_rst=!phy_init_done; 180 assign ddr_rst=!phy_init_done; 182 181 183 182 /*oct_alt_oct_power_f4c oct … … 190 189 191 190 always @( * ) 192 case(cmd_out[1:0]) 193 2'b00:mask_data<={24'h000000,wr_dout[71:64]}; 194 2'b01:mask_data<={16'h0000,wr_dout[71:64],8'h00}; 195 2'b10:mask_data<={8'h00,wr_dout[71:64],16'h0000}; 196 2'b11:mask_data<={wr_dout[71:64],24'h000000}; 191 case(cmd_out[0]) 192 1'b0:mask_data<={8'h00,wr_dout[71:64]}; 193 1'b1:mask_data<={wr_dout[71:64],8'h00}; 197 194 endcase 198 195 … … 304 301 305 302 always @( * ) 306 case(wb_adr_i[4:3]) 307 2'b00:wb_dat_o<=rd_data_fifo_out_d[63:0]; 308 2'b01:wb_dat_o<=rd_data_fifo_out_d[127:64]; 309 2'b10:wb_dat_o<=rd_data_fifo_out_d[191:128]; 310 2'b11:wb_dat_o<=rd_data_fifo_out_d[255:192]; 303 case(wb_adr_i[3]) 304 1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0]; 305 1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64]; 311 306 endcase 312 307 313 308 always @(posedge wb_clk_i or posedge wb_rst_i) 314 309 if(wb_rst_i) 315 rd_addr_cache<=24'hFFFFFF; 310 begin 311 //written<=0; 312 rd_addr_cache<=24'hFFFFFF; 313 end 316 314 else 317 315 begin -
trunk/os2wb/os2wb.v
r17 r22 119 119 `define PCX_REQ_CAS_COMPARE 5'b11111 120 120 121 `define MEM_SIZE 64'h00000000_10000000 122 121 //`define MEM_SIZE 64'h00000000_10000000 //256 MB 122 //`define MEM_SIZE 64'h00000000_00100000 //1MB 123 `define MEM_SIZE 64'h00000000_00001000 //256KB 124 125 // sal: escludo test della DRAM `define TEST_DRAM 1 123 126 `define TEST_DRAM 1 124 127 `define DEBUGGING 1 … … 178 181 pcx_fifo pcx_fifo_inst( 179 182 .clk(clk), 180 183 .rst(!rstn), 181 184 .din({pcx_atom_1,pcx_req_1,pcx_data}), 182 185 .rd_en(fifo_rd), 183 186 .wr_en((pcx_req_1!=5'b00000 && pcx_data[123]) || (pcx_atom_2 && pcx_data_123_d)), 184 187 .empty(pcx_fifo_empty), 188 .full(), 185 189 .dout(pcx_data_fifo) 186 190 ); … … 209 213 if(rstn==0) 210 214 begin 215 //$display("INFO: OS2WB: RST_DRAM at %t",$time); 211 216 if(`TEST_DRAM) 212 217 state<=`TEST_DRAM_1; 213 218 else 214 219 state<=`INIT_DRAM_1; // DRAM initialization is mandatory! 215 220 cpx_ready<=0; 216 221 fifo_rd<=0; … … 230 235 `TEST_DRAM_1: 231 236 begin 237 $display("INFO: OS2WB: TEST_DRAM_1"); 232 238 wb_cycle<=1; 233 239 wb_strobe<=1; … … 239 245 if(wb_ack) 240 246 begin 247 $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); 241 248 wb_strobe<=0; 242 249 if(wb_addr<`MEM_SIZE-8) … … 258 265 `TEST_DRAM_3: 259 266 begin 267 $display("INFO: OS2WB: TEST_DRAM_3"); 260 268 wb_cycle<=1; 261 269 wb_strobe<=1; … … 266 274 if(wb_ack) 267 275 begin 276 $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); 268 277 wb_strobe<=0; 269 278 if(wb_addr<`MEM_SIZE-8) … … 274 283 state<=`TEST_DRAM_3; 275 284 end 285 else 286 $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); 287 276 288 end 277 289 else 278 290 begin 291 $display("INFO: OS2WB: INIT_DRAM at %t",$time); 279 292 state<=`INIT_DRAM_1; 280 293 wb_cycle<=0; … … 300 313 if(wb_addr<`MEM_SIZE-8) 301 314 begin 315 //for debug 316 // if (wb_addr[10:3]==8'b0) 317 // $display("INFO: OS2WB: INIT_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); 318 // 302 319 wb_addr[31:0]<=wb_addr[31:0]+8; 303 320 pcx_packet_d[64+11:64+4]<=pcx_packet_d[64+11:64+4]+1; // Address for cachedir init … … 306 323 else 307 324 begin 325 $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); 308 326 state<=`WAKEUP; 309 327 wb_cycle<=0; … … 349 367 if(`DEBUGGING) 350 368 begin 369 $display("INFO: OS2WB: GOT_PCX_REQ"); 351 370 wb_sel[1:0]<=pcx_packet[113:112]; 352 371 wb_sel[2]<=1; … … 1236 1255 1237 1256 .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), 1238 .address_b({2'b0 1,icache_index}),1257 .address_b({2'b0,icache_index}), 1239 1258 .data_b(icache_data), 1240 1259 .q_b(icache1_do) … … 1245 1264 .enable(dir_en), 1246 1265 .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init), 1247 .address_a({ 1'b0,icache_index}),1266 .address_a({2'b0,icache_index}), 1248 1267 .data_a(icache_data), 1249 1268 .q_a(icache2_do), 1250 1269 1251 1270 .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init), 1252 .address_b({ 1'b1,icache_index}),1271 .address_b({2'b0,icache_index}), 1253 1272 .data_b(icache_data), 1254 1273 .q_b(icache3_do) -
trunk/os2wb/s1_top.v
r10 r22 140 140 //.spc_scanout0(spc_scanout0), 141 141 //.spc_scanout1(spc_scanout1), 142 //.tst_ctu_mbist_done(tst_ctu_mbist_done), 143 //.tst_ctu_mbist_fail(tst_ctu_mbist_fail), 144 //.spc_efc_ifuse_data(spc_efc_ifuse_data), 145 //.spc_efc_dfuse_data(spc_efc_dfuse_data), 146 147 // Wires connected to SPARC Core inputs 142 //sal: controllare se in sintesi questi 4 segnali danno problemi!!! 143 .tst_ctu_mbist_done(), 144 .tst_ctu_mbist_fail(), 145 .spc_efc_ifuse_data(), 146 .spc_efc_dfuse_data(), 147 // 148 // Wires connected to SPARC Core inputs 148 149 .pcx_spc_grant_px(pcx_spc_grant_px), 149 150 .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2), … … 273 274 .fp_rdy(fp_rdy!=8'h00), 274 275 275 .eth_int( 0/*eth_irq_i*/)276 .eth_int(1'b0/*eth_irq_i*/) 276 277 ); 277 278 … … 295 296 .ctu_tst_short_chain(ctu_tst_short_chain), 296 297 297 .si( 0),298 .si(1'b0), 298 299 .so() 299 300 ); -
trunk/sim/sim_tb_top.v
r10 r22 289 289 .CS_WIDTH (CS_WIDTH), 290 290 .CS_BITS (CS_BITS), 291 .DM_WIDTH 291 .DM_WIDTH (DM_WIDTH), 292 292 .DQ_WIDTH (DQ_WIDTH), 293 293 .DQ_PER_DQS (DQ_PER_DQS), … … 318 318 .SIM_ONLY (SIM_ONLY), 319 319 .RST_ACT_LOW (RST_ACT_LOW), 320 .CLK_TYPE 321 .DLL_FREQ_MODE 320 .CLK_TYPE (CLK_TYPE), 321 .DLL_FREQ_MODE (DLL_FREQ_MODE), 322 322 .CLK_PERIOD (CLK_PERIOD) 323 323 ) … … 341 341 .ddr2_ba (ddr2_ba_fpga), 342 342 .ddr2_a (ddr2_address_fpga), 343 .error (error),343 //.error (error), 344 344 345 345 -
trunk/sim/simula.do
r17 r22 45 45 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl 46 46 47 add wave sim:/tb_top/W1_inst/dram_wb_inst/* 48 #exit 47 49 pause 48 50 onerror {resume} -
trunk/sim/tb_top.v
r17 r22 14 14 localparam real TCYC_200 = 5.0; 15 15 parameter RST_ACT_LOW = 1; // =1 for active low reset, =0 for active high 16 localparam real TPROP_DQS = 0.01; // Delay for DQS signal during Write Operation 17 localparam real TPROP_DQS_RD = 0.01; // Delay for DQS signal during Read Operation 18 localparam real TPROP_PCB_CTRL = 0.01; // Delay for Address and Ctrl signals 19 localparam real TPROP_PCB_DATA = 0.01; // Delay for data signal during Write operation 20 localparam real TPROP_PCB_DATA_RD = 0.01; // Delay for data signal during Read operation 16 21 17 22 … … 32 37 wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; 33 38 wire [7:0] ddr2_dm_sdram; 34 wire ddr2_clk_sdram; 35 wire ddr2_clk_n_sdram; 36 wire [12:0] ddr2_address_sdram; 37 wire [1:0] ddr2_ba_sdram; 38 wire ddr2_ras_n_sdram; 39 wire ddr2_cas_n_sdram; 40 wire ddr2_we_n_sdram; 41 wire [CS_WIDTH-1:0] ddr2_cs_n_sdram; 42 wire ddr2_cke_sdram; 43 wire [ODT_WIDTH-1:0] ddr2_odt_sdram; 39 reg [7:0] ddr2_dm_sdram_tmp; 40 reg ddr2_clk_sdram; 41 reg ddr2_clk_n_sdram; 42 reg [12:0] ddr2_address_sdram; 43 reg [1:0] ddr2_ba_sdram; 44 reg ddr2_ras_n_sdram; 45 reg ddr2_cas_n_sdram; 46 reg ddr2_we_n_sdram; 47 reg [CS_WIDTH-1:0] ddr2_cs_n_sdram; 48 reg ddr2_cke_sdram; 49 reg [ODT_WIDTH-1:0] ddr2_odt_sdram; 50 51 wire [DQ_WIDTH-1:0] ddr2_dq_fpga; 52 wire [DQS_WIDTH-1:0] ddr2_dqs_fpga; 53 wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga; 54 wire [7:0] ddr2_dm_fpga; 55 wire ddr2_clk_fpga; 56 wire ddr2_clk_n_fpga; 57 wire [12:0] ddr2_address_fpga; 58 wire [1:0] ddr2_ba_fpga; 59 wire ddr2_ras_n_fpga; 60 wire ddr2_cas_n_fpga; 61 wire ddr2_we_n_fpga; 62 wire [CS_WIDTH-1:0] ddr2_cs_n_fpga; 63 wire ddr2_cke_fpga; 64 wire [ODT_WIDTH-1:0] ddr2_odt_fpga; 65 44 66 45 67 wire stx; … … 57 79 58 80 // Create VCD trace file 59 $dumpfile("trace.vcd");60 $dumpvars();81 // $dumpfile("trace.vcd"); 82 // $dumpvars(); 61 83 62 84 // Run the simulation … … 65 87 // #1000 66 88 // sys_reset <= 1'b0; 67 # 10000089 #700_000 68 90 $display("INFO: TBENCH: Completed simulation!"); 69 91 $finish; … … 109 131 110 132 // ddr3 memory interface 111 .ddr3_dq (ddr2_dq_ sdram),112 .ddr3_dqs (ddr2_dqs_ n_sdram),113 .ddr3_dqs_n (ddr2_dqs_n_ sdram),114 .ddr3_ck (ddr2_clk_ sdram),115 .ddr3_ck_n (ddr2_clk_n_ sdram),116 .ddr3_a (ddr2_address_ sdram),117 .ddr3_ba (ddr2_ba_ sdram), //FIXME118 .ddr3_ras_n (ddr2_ras_n_ sdram),119 .ddr3_cas_n (ddr2_cas_n_ sdram),120 .ddr3_we_n (ddr2_we_n_ sdram),121 .ddr3_cs_n (ddr2_cs_n_ sdram),122 .ddr3_odt (ddr2_odt_ sdram),123 .ddr3_ce (ddr2_cke_ sdram),124 .ddr3_dm (ddr2_dm_ sdram),133 .ddr3_dq (ddr2_dq_fpga), 134 .ddr3_dqs (ddr2_dqs_fpga), 135 .ddr3_dqs_n (ddr2_dqs_n_fpga), 136 .ddr3_ck (ddr2_clk_fpga), 137 .ddr3_ck_n (ddr2_clk_n_fpga), 138 .ddr3_a (ddr2_address_fpga), 139 .ddr3_ba (ddr2_ba_fpga), //FIXME 140 .ddr3_ras_n (ddr2_ras_n_fpga), 141 .ddr3_cas_n (ddr2_cas_n_fpga), 142 .ddr3_we_n (ddr2_we_n_fpga), 143 .ddr3_cs_n (ddr2_cs_n_fpga), 144 .ddr3_odt (ddr2_odt_fpga), 145 .ddr3_ce (ddr2_cke_fpga), 146 .ddr3_dm (ddr2_dm_fpga), 125 147 126 148 // Console interface … … 156 178 .flash_rst(flash_rst) 157 179 ); 180 181 //DDR2 model 182 // 183 184 always @( * ) begin 185 ddr2_clk_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_fpga; 186 ddr2_clk_n_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_n_fpga; 187 ddr2_address_sdram <= #(TPROP_PCB_CTRL) ddr2_address_fpga; 188 ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga; 189 ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga; 190 ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga; 191 ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga; 192 ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga; 193 ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga; 194 ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga; 195 ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation 196 end 197 198 assign ddr2_dm_sdram = ddr2_dm_sdram_tmp; 199 200 genvar dqwd; 201 generate 202 for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay 203 WireDelay # 204 ( 205 .Delay_g (TPROP_PCB_DATA), 206 .Delay_rd (TPROP_PCB_DATA_RD) 207 ) 208 u_delay_dq 209 ( 210 .A (ddr2_dq_fpga[dqwd]), 211 .B (ddr2_dq_sdram[dqwd]), 212 .reset (sys_rst_n) 213 ); 214 end 215 endgenerate 216 217 218 genvar dqswd; 219 generate 220 for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay 221 WireDelay # 222 ( 223 .Delay_g (TPROP_DQS), 224 .Delay_rd (TPROP_DQS_RD) 225 ) 226 u_delay_dqs 227 ( 228 .A (ddr2_dqs_fpga[dqswd]), 229 .B (ddr2_dqs_sdram[dqswd]), 230 .reset (sys_rst_n) 231 ); 232 233 WireDelay # 234 ( 235 .Delay_g (TPROP_DQS), 236 .Delay_rd (TPROP_DQS_RD) 237 ) 238 u_delay_dqs_n 239 ( 240 .A (ddr2_dqs_n_fpga[dqswd]), 241 .B (ddr2_dqs_n_sdram[dqswd]), 242 .reset (sys_rst_n) 243 ); 244 end 245 endgenerate 246 158 247 // if the data width is multiple of 16 159 248 //for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs
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