source: XOpenSparcT1/trunk/sim/tb_top.v @ 34

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(edit) @23   14 years pntsvt00 supera il test di write e read dalla DDR
(edit) @22   14 years pntsvt00 checkpoint: la DDR effettua l'init
(edit) @17   14 years pntsvt00 la simulazione legge dalla flash
(edit) @16   14 years pntsvt00 ora la simulazione parte
(add) @11   14 years pntsvt00 commit versione simulabile
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