source: XOpenSparcT1/trunk/sim @ 34

Name Size Rev Age Author Last Change
../
wiredly.v 4.3 KB 10   14 years pntsvt00 versione sintetizzabile
tb_top.v 8.6 KB 23   14 years pntsvt00 supera il test di write e read dalla DDR
simula.do 3.2 KB 34   14 years pntsvt00 versione pre-pre-alpha
sim_tb_top.vhd 32.5 KB 10   14 years pntsvt00 versione sintetizzabile
sim_tb_top.v 26.5 KB 22   14 years pntsvt00 checkpoint: la DDR effettua l'init
memory.hex 8.1 KB 30   14 years pntsvt00 aggiornata tool-chain
flash.v 1.8 KB 26   14 years pntsvt00 checkpoint: baco con store consecutivi
ddr2_model_parameters.vh 108.8 KB 10   14 years pntsvt00 versione sintetizzabile
ddr2_model.v 108.4 KB 10   14 years pntsvt00 versione sintetizzabile
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