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trunk/sim/flash.v
r21 r26 42 42 $readmemh(memfilename, mem); 43 43 $display("INFO: MEMH %m: Memory initialization completed"); 44 //for(i=0; i<=1023; i=i+1) $display("mem_i = %x",mem[i]) ; 44 45 end 45 46 `endif 46 47 47 48 assign flash_data = !flash_oen ? data :16'hzzzz; 48 49 49 50 50 always @(posedge flash_clk) begin 51 51 // Read cycle 52 52 if (!flash_oen & flash_wen) 53 data <= mem[flash_addr]; 53 begin 54 //$display("INFO: flash: read from address %x data %x",flash_addr, mem[flash_addr]); 55 data <= mem[flash_addr]; 56 end 54 57 else // Write cycle 55 if (flash_oen & !flash_wen) mem[flash_addr] <= flash_data; 56 end 58 if (flash_oen & !flash_wen) 59 $display("INFO: flash: write to address %x data %x (now disabled)",flash_addr,flash_data); 60 //mem[flash_addr] <= flash_data; FIXME: errouneous spourious writes in flash 61 end 57 62 endmodule 58 63 -
trunk/sim/simula.do
r22 r26 1 1 #start with: vsim -c -do simula.do 2 2 3 set DEFINE +define+DEBUG+FPGA_SYN 4 #+FPGA_NEW_IRF 5 set INCLUDEDIR +incdir+../T1-common/include/ 3 6 vlib work 4 7 … … 7 10 #Compile all modules# 8 11 9 vlog +incdir+../T1-common/include/../T1-common/common/*.v10 vlog +incdir+../T1-common/include/../Top/*.v11 vlog +incdir+../OC-UART +incdir+../T1-common/include/../OC-UART/*.v12 vlog +incdir+../T1-common/include/../NOR-flash/*.v13 vlog +incdir+../T1-common/include/../os2wb/*.v14 vlog +incdir+../T1-common/include/../T1-common/m1/*.V15 vlog +define+FPGA_SYN +incdir+../T1-common/include/../T1-common/srams/*.v16 vlog +incdir+../T1-common/include/../T1-common/u1/*.V17 vlog +incdir+../T1-common/include/ ../T1-FPU/*.v18 vlog +incdir+../T1-common/include/+incdir+../WB ../WB/*.v19 vlog +incdir+../T1-common/include/../WB2ALTDDR3/*.v20 vlog +incdir+../T1-common/include/../Xilinx/*.v21 vlog +incdir+../T1-common/include/../T1-CPU/exu/*.v22 vlog +incdir+../T1-common/include/../T1-CPU/ffu/*.v23 vlog +incdir+../T1-common/include/../T1-CPU/ifu/*.v24 vlog +incdir+../T1-common/include/../T1-CPU/lsu/*.v25 vlog +incdir+../T1-common/include/../T1-CPU/mul/*.v26 vlog +incdir+../T1-common/include/../T1-CPU/rtl/*.v27 vlog +incdir+../T1-common/include/../T1-CPU/spu/*.v28 vlog +incdir+../T1-common/include/../T1-CPU/tlu/*.v12 vlog $DEFINE $INCLUDEDIR ../T1-common/common/*.v 13 vlog $DEFINE $INCLUDEDIR ../Top/*.v 14 vlog $DEFINE +incdir+../OC-UART $INCLUDEDIR ../OC-UART/*.v 15 vlog $DEFINE $INCLUDEDIR ../NOR-flash/*.v 16 vlog $DEFINE $INCLUDEDIR ../os2wb/*.v 17 vlog $DEFINE $INCLUDEDIR ../T1-common/m1/*.V 18 vlog $DEFINE $INCLUDEDIR ../T1-common/srams/*.v 19 vlog $DEFINE $INCLUDEDIR ../T1-common/u1/*.V 20 vlog $DEFINE $INCLUDEDIR/ ../T1-FPU/*.v 21 vlog $DEFINE $INCLUDEDIR +incdir+../WB ../WB/*.v 22 vlog $DEFINE $INCLUDEDIR ../WB2ALTDDR3/*.v 23 vlog $DEFINE $INCLUDEDIR ../Xilinx/*.v 24 vlog $DEFINE $INCLUDEDIR ../T1-CPU/exu/*.v 25 vlog $DEFINE $INCLUDEDIR ../T1-CPU/ffu/*.v 26 vlog $DEFINE $INCLUDEDIR ../T1-CPU/ifu/*.v 27 vlog $DEFINE $INCLUDEDIR ../T1-CPU/lsu/*.v 28 vlog $DEFINE $INCLUDEDIR ../T1-CPU/mul/*.v 29 vlog $DEFINE $INCLUDEDIR ../T1-CPU/rtl/*.v 30 vlog $DEFINE $INCLUDEDIR ../T1-CPU/spu/*.v 31 vlog $DEFINE $INCLUDEDIR ../T1-CPU/tlu/*.v 29 32 30 33 #Compile files in sim folder (excluding model parameter file)#
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